OTBN Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	otbn_smoke	8.000s	82.790us	1	1	100.00
V1	single_binary	otbn_single	14.000s	155.320us	1	1	100.00
V1	csr_hw_reset	otbn_csr_hw_reset	4.000s	40.265us	1	1	100.00
V1	csr_rw	otbn_csr_rw	3.000s	41.288us	1	1	100.00
V1	csr_bit_bash	otbn_csr_bit_bash	7.000s	138.751us	1	1	100.00
V1	csr_aliasing	otbn_csr_aliasing	4.000s	19.437us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	otbn_csr_mem_rw_with_rand_reset	5.000s	24.648us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	otbn_csr_rw	3.000s	41.288us	1	1	100.00
		otbn_csr_aliasing	4.000s	19.437us	1	1	100.00
V1	mem_walk	otbn_mem_walk	37.000s	1914.662us	1	1	100.00
V1	mem_partial_access	otbn_mem_partial_access	11.000s	124.564us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	reset_recovery	otbn_reset	18.000s	213.318us	1	1	100.00
V2	multi_error	otbn_multi_err	67.000s	368.347us	1	1	100.00
V2	back_to_back	otbn_multi	55.000s	1708.433us	1	1	100.00
V2	stress_all	otbn_stress_all	96.000s	839.272us	1	1	100.00
V2	lc_escalation	otbn_escalate	6.000s	21.306us	1	1	100.00
V2	zero_state_err_urnd	otbn_zero_state_err_urnd	8.000s	63.222us	1	1	100.00
V2	sw_errs_fatal_chk	otbn_sw_errs_fatal_chk	23.000s	103.698us	1	1	100.00
V2	alert_test	otbn_alert_test	3.000s	40.444us	1	1	100.00
V2	intr_test	otbn_intr_test	3.000s	32.642us	1	1	100.00
V2	tl_d_oob_addr_access	otbn_tl_errors	4.000s	142.774us	1	1	100.00
V2	tl_d_illegal_access	otbn_tl_errors	4.000s	142.774us	1	1	100.00
V2	tl_d_outstanding_access	otbn_csr_hw_reset	4.000s	40.265us	1	1	100.00
		otbn_csr_rw	3.000s	41.288us	1	1	100.00
		otbn_csr_aliasing	4.000s	19.437us	1	1	100.00
		otbn_same_csr_outstanding	3.000s	43.822us	1	1	100.00
V2	tl_d_partial_access	otbn_csr_hw_reset	4.000s	40.265us	1	1	100.00
		otbn_csr_rw	3.000s	41.288us	1	1	100.00
		otbn_csr_aliasing	4.000s	19.437us	1	1	100.00
		otbn_same_csr_outstanding	3.000s	43.822us	1	1	100.00
V2		TOTAL			11	11	100.00
V2S	mem_integrity	otbn_imem_err	5.000s	131.809us	1	1	100.00
		otbn_dmem_err	17.000s	81.961us	1	1	100.00
V2S	internal_integrity	otbn_alu_bignum_mod_err	5.000s	331.245us	1	1	100.00
		otbn_controller_ispr_rdata_err	7.000s	202.350us	1	1	100.00
		otbn_mac_bignum_acc_err	6.000s	214.049us	1	1	100.00
		otbn_urnd_err	6.000s	14.221us	1	1	100.00
V2S	illegal_bus_access	otbn_illegal_mem_acc	5.000s	115.905us	1	1	100.00
V2S	otbn_mem_gnt_acc_err	otbn_mem_gnt_acc_err	4.000s	50.998us	1	1	100.00
V2S	otbn_non_sec_partial_wipe	otbn_partial_wipe	4.000s	10.515us	1	1	100.00
V2S	tl_intg_err	otbn_sec_cm	170.000s	2131.241us	1	1	100.00
		otbn_tl_intg_err	15.000s	98.288us	1	1	100.00
V2S	passthru_mem_tl_intg_err	otbn_passthru_mem_tl_intg_err	13.000s	68.059us	0	1	0.00
V2S	prim_fsm_check	otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	prim_count_check	otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	sec_cm_mem_scramble	otbn_smoke	8.000s	82.790us	1	1	100.00
V2S	sec_cm_data_mem_integrity	otbn_dmem_err	17.000s	81.961us	1	1	100.00
V2S	sec_cm_instruction_mem_integrity	otbn_imem_err	5.000s	131.809us	1	1	100.00
V2S	sec_cm_bus_integrity	otbn_tl_intg_err	15.000s	98.288us	1	1	100.00
V2S	sec_cm_controller_fsm_global_esc	otbn_escalate	6.000s	21.306us	1	1	100.00
V2S	sec_cm_controller_fsm_local_esc	otbn_imem_err	5.000s	131.809us	1	1	100.00
		otbn_dmem_err	17.000s	81.961us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	63.222us	1	1	100.00
		otbn_illegal_mem_acc	5.000s	115.905us	1	1	100.00
		otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	sec_cm_controller_fsm_sparse	otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	sec_cm_scramble_key_sideload	otbn_single	14.000s	155.320us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_local_esc	otbn_imem_err	5.000s	131.809us	1	1	100.00
		otbn_dmem_err	17.000s	81.961us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	63.222us	1	1	100.00
		otbn_illegal_mem_acc	5.000s	115.905us	1	1	100.00
		otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	sec_cm_scramble_ctrl_fsm_sparse	otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_global_esc	otbn_escalate	6.000s	21.306us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_local_esc	otbn_imem_err	5.000s	131.809us	1	1	100.00
		otbn_dmem_err	17.000s	81.961us	1	1	100.00
		otbn_zero_state_err_urnd	8.000s	63.222us	1	1	100.00
		otbn_illegal_mem_acc	5.000s	115.905us	1	1	100.00
		otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_fsm_sparse	otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	sec_cm_data_reg_sw_sca	otbn_single	14.000s	155.320us	1	1	100.00
V2S	sec_cm_ctrl_redun	otbn_ctrl_redun	6.000s	25.494us	1	1	100.00
V2S	sec_cm_pc_ctrl_flow_redun	otbn_pc_ctrl_flow_redun	4.000s	12.674us	1	1	100.00
V2S	sec_cm_rnd_bus_consistency	otbn_rnd_sec_cm	128.000s	766.090us	1	1	100.00
V2S	sec_cm_rnd_rng_digest	otbn_rnd_sec_cm	128.000s	766.090us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_integrity	otbn_rf_base_intg_err	5.000s	15.352us	1	1	100.00
V2S	sec_cm_rf_base_data_reg_sw_glitch_detect	otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	sec_cm_stack_wr_ptr_ctr_redun	otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_integrity	otbn_rf_bignum_intg_err	7.000s	54.144us	1	1	100.00
V2S	sec_cm_rf_bignum_data_reg_sw_glitch_detect	otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	sec_cm_loop_stack_ctr_redun	otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S	sec_cm_loop_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	23.165us	1	1	100.00
V2S	sec_cm_call_stack_addr_integrity	otbn_stack_addr_integ_chk	8.000s	23.165us	1	1	100.00
V2S	sec_cm_start_stop_ctrl_state_consistency	otbn_sec_wipe_err	6.000s	18.831us	1	1	100.00
V2S	sec_cm_data_mem_sec_wipe	otbn_single	14.000s	155.320us	1	1	100.00
V2S	sec_cm_instruction_mem_sec_wipe	otbn_single	14.000s	155.320us	1	1	100.00
V2S	sec_cm_data_reg_sw_sec_wipe	otbn_single	14.000s	155.320us	1	1	100.00
V2S	sec_cm_write_mem_integrity	otbn_multi	55.000s	1708.433us	1	1	100.00
V2S	sec_cm_ctrl_flow_count	otbn_single	14.000s	155.320us	1	1	100.00
V2S	sec_cm_ctrl_flow_sca	otbn_single	14.000s	155.320us	1	1	100.00
V2S	sec_cm_data_mem_sw_noaccess	otbn_sw_no_acc	6.000s	119.999us	1	1	100.00
V2S	sec_cm_key_sideload	otbn_single	14.000s	155.320us	1	1	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	otbn_sec_cm	170.000s	2131.241us	1	1	100.00
V2S		TOTAL			19	20	95.00
V3	stress_all_with_rand_reset	otbn_stress_all_with_rand_reset	262.000s	11288.618us	0	1	0.00
V3		TOTAL			0	1	0.00
		TOTAL			39	41	95.12

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.72	99.47	93.65	99.58	91.41	92.04	94.87	88.93	97.01

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1230) [otbn_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:

  • Test otbn_stress_all_with_rand_reset has 1 failures.

    • 0.otbn_stress_all_with_rand_reset.95102926204732666430241444582776316578251411197381366297682635104171918841834
      Line 222, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 11288617810 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.otbn_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 11288617810 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL (otbn_scoreboard.sv:550) scoreboard [scoreboard] We saw a STATUS change * cycles ago that implied we'd get a fatal alert but it still hasn't arrived. has 1 failures:

  • Test otbn_passthru_mem_tl_intg_err has 1 failures.

    • 0.otbn_passthru_mem_tl_intg_err.87576870942272750544348069871024200752307684154053667977408511430465517057475
      Line 108, in log /nightly/current_run/scratch/master/otbn-sim-xcelium/0.otbn_passthru_mem_tl_intg_err/latest/run.log

        UVM_FATAL @  68059321 ps: (otbn_scoreboard.sv:550) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] We saw a STATUS change 30 cycles ago that implied we'd get a fatal alert but it still hasn't arrived.
        UVM_INFO @  68059321 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---