PATTGEN Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pattgen_smoke	14.000s	282.701us	1	1	100.00
V1	csr_hw_reset	pattgen_csr_hw_reset	1.000s	49.551us	1	1	100.00
V1	csr_rw	pattgen_csr_rw	1.000s	39.996us	1	1	100.00
V1	csr_bit_bash	pattgen_csr_bit_bash	2.000s	202.084us	1	1	100.00
V1	csr_aliasing	pattgen_csr_aliasing	1.000s	28.431us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	pattgen_csr_mem_rw_with_rand_reset	1.000s	39.950us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pattgen_csr_rw	1.000s	39.996us	1	1	100.00
		pattgen_csr_aliasing	1.000s	28.431us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	perf	pattgen_perf	547.000s	148732.870us	1	1	100.00
V2	cnt_rollover	cnt_rollover	12.000s	44.223us	1	1	100.00
V2	error	pattgen_error	13.000s	35.326us	1	1	100.00
V2	stress_all	pattgen_stress_all	6.000s	100.187us	1	1	100.00
V2	alert_test	pattgen_alert_test	2.000s	14.529us	1	1	100.00
V2	intr_test	pattgen_intr_test	1.000s	26.975us	1	1	100.00
V2	tl_d_oob_addr_access	pattgen_tl_errors	2.000s	323.420us	1	1	100.00
V2	tl_d_illegal_access	pattgen_tl_errors	2.000s	323.420us	1	1	100.00
V2	tl_d_outstanding_access	pattgen_csr_hw_reset	1.000s	49.551us	1	1	100.00
		pattgen_csr_rw	1.000s	39.996us	1	1	100.00
		pattgen_csr_aliasing	1.000s	28.431us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	60.240us	1	1	100.00
V2	tl_d_partial_access	pattgen_csr_hw_reset	1.000s	49.551us	1	1	100.00
		pattgen_csr_rw	1.000s	39.996us	1	1	100.00
		pattgen_csr_aliasing	1.000s	28.431us	1	1	100.00
		pattgen_same_csr_outstanding	1.000s	60.240us	1	1	100.00
V2		TOTAL			8	8	100.00
V2S	tl_intg_err	pattgen_sec_cm	10.000s	41.079us	1	1	100.00
		pattgen_tl_intg_err	1.000s	237.535us	1	1	100.00
V2S	sec_cm_bus_integrity	pattgen_tl_intg_err	1.000s	237.535us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	pattgen_stress_all_with_rand_reset	51.000s	8344.221us	0	1	0.00
V3		TOTAL			0	1	0.00
	Unmapped tests	pattgen_inactive_level	12.000s	69.489us	1	1	100.00
		TOTAL			17	18	94.44

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
98.23	100.00	100.00	100.00	96.44	96.61	--	96.95	89.42

Failure Buckets

• UVM_ERROR (cip_base_vseq.sv:1230) [pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 1 failures:
  • Test pattgen_stress_all_with_rand_reset has 1 failures.

    • 0.pattgen_stress_all_with_rand_reset.17958595677452810615428844446641340913213998213618764716377256968322870229833
      Line 144, in log /nightly/current_run/scratch/master/pattgen-sim-xcelium/0.pattgen_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 454241224 ps: (cip_base_vseq.sv:1230) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_ERROR @ 454241725 ps: (cip_base_vseq.sv:1143) [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq] Check failed (cfg.can_reset_with_csr_accesses || !has_outstanding_access()) Trying to trigger a reset with outstanding CSR items.
        UVM_INFO @ 454241725 ps: (cip_base_vseq.sv:1146) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]
        Issuing reset for run 2/10
        UVM_INFO @ 454441725 ps: (cip_base_vseq.sv:1167) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.pattgen_common_vseq]