ROM_CTRL/32KB Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	rom_ctrl_smoke	6.290s	1000.831us	2	2	100.00
V1	csr_hw_reset	rom_ctrl_csr_hw_reset	9.020s	298.624us	2	2	100.00
V1	csr_rw	rom_ctrl_csr_rw	5.750s	212.557us	2	2	100.00
V1	csr_bit_bash	rom_ctrl_csr_bit_bash	5.830s	213.162us	2	2	100.00
V1	csr_aliasing	rom_ctrl_csr_aliasing	5.250s	725.689us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	rom_ctrl_csr_mem_rw_with_rand_reset	7.120s	305.926us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rom_ctrl_csr_rw	5.750s	212.557us	2	2	100.00
		rom_ctrl_csr_aliasing	5.250s	725.689us	2	2	100.00
V1	mem_walk	rom_ctrl_mem_walk	5.770s	205.789us	2	2	100.00
V1	mem_partial_access	rom_ctrl_mem_partial_access	6.730s	289.851us	2	2	100.00
V1		TOTAL			16	16	100.00
V2	max_throughput_chk	rom_ctrl_max_throughput_chk	7.880s	303.431us	2	2	100.00
V2	stress_all	rom_ctrl_stress_all	19.400s	2228.124us	2	2	100.00
V2	kmac_err_chk	rom_ctrl_kmac_err_chk	13.410s	2300.805us	2	2	100.00
V2	alert_test	rom_ctrl_alert_test	6.280s	4151.800us	2	2	100.00
V2	tl_d_oob_addr_access	rom_ctrl_tl_errors	8.430s	626.967us	2	2	100.00
V2	tl_d_illegal_access	rom_ctrl_tl_errors	8.430s	626.967us	2	2	100.00
V2	tl_d_outstanding_access	rom_ctrl_csr_hw_reset	9.020s	298.624us	2	2	100.00
		rom_ctrl_csr_rw	5.750s	212.557us	2	2	100.00
		rom_ctrl_csr_aliasing	5.250s	725.689us	2	2	100.00
		rom_ctrl_same_csr_outstanding	6.250s	215.776us	2	2	100.00
V2	tl_d_partial_access	rom_ctrl_csr_hw_reset	9.020s	298.624us	2	2	100.00
		rom_ctrl_csr_rw	5.750s	212.557us	2	2	100.00
		rom_ctrl_csr_aliasing	5.250s	725.689us	2	2	100.00
		rom_ctrl_same_csr_outstanding	6.250s	215.776us	2	2	100.00
V2		TOTAL			12	12	100.00
V2S	corrupt_sig_fatal_chk	rom_ctrl_corrupt_sig_fatal_chk	141.500s	44466.889us	2	2	100.00
V2S	passthru_mem_tl_intg_err	rom_ctrl_passthru_mem_tl_intg_err	38.430s	13828.816us	2	2	100.00
V2S	tl_intg_err	rom_ctrl_sec_cm	451.530s	1238.535us	0	2	0.00
		rom_ctrl_tl_intg_err	93.560s	1707.898us	2	2	100.00
V2S	prim_fsm_check	rom_ctrl_sec_cm	451.530s	1238.535us	0	2	0.00
V2S	prim_count_check	rom_ctrl_sec_cm	451.530s	1238.535us	0	2	0.00
V2S	sec_cm_checker_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	141.500s	44466.889us	2	2	100.00
V2S	sec_cm_checker_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	141.500s	44466.889us	2	2	100.00
V2S	sec_cm_checker_fsm_local_esc	rom_ctrl_corrupt_sig_fatal_chk	141.500s	44466.889us	2	2	100.00
V2S	sec_cm_compare_ctrl_flow_consistency	rom_ctrl_corrupt_sig_fatal_chk	141.500s	44466.889us	2	2	100.00
V2S	sec_cm_compare_ctr_consistency	rom_ctrl_corrupt_sig_fatal_chk	141.500s	44466.889us	2	2	100.00
V2S	sec_cm_compare_ctr_redun	rom_ctrl_sec_cm	451.530s	1238.535us	0	2	0.00
V2S	sec_cm_fsm_sparse	rom_ctrl_sec_cm	451.530s	1238.535us	0	2	0.00
V2S	sec_cm_mem_scramble	rom_ctrl_smoke	6.290s	1000.831us	2	2	100.00
V2S	sec_cm_mem_digest	rom_ctrl_smoke	6.290s	1000.831us	2	2	100.00
V2S	sec_cm_intersig_mubi	rom_ctrl_smoke	6.290s	1000.831us	2	2	100.00
V2S	sec_cm_bus_integrity	rom_ctrl_tl_intg_err	93.560s	1707.898us	2	2	100.00
V2S	sec_cm_bus_local_esc	rom_ctrl_corrupt_sig_fatal_chk	141.500s	44466.889us	2	2	100.00
		rom_ctrl_kmac_err_chk	13.410s	2300.805us	2	2	100.00
V2S	sec_cm_mux_mubi	rom_ctrl_corrupt_sig_fatal_chk	141.500s	44466.889us	2	2	100.00
V2S	sec_cm_mux_consistency	rom_ctrl_corrupt_sig_fatal_chk	141.500s	44466.889us	2	2	100.00
V2S	sec_cm_ctrl_redun	rom_ctrl_corrupt_sig_fatal_chk	141.500s	44466.889us	2	2	100.00
V2S	sec_cm_ctrl_mem_integrity	rom_ctrl_passthru_mem_tl_intg_err	38.430s	13828.816us	2	2	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	rom_ctrl_sec_cm	451.530s	1238.535us	0	2	0.00
V2S		TOTAL			6	8	75.00
V3	stress_all_with_rand_reset	rom_ctrl_stress_all_with_rand_reset	68.040s	10322.650us	2	2	100.00
V3		TOTAL			2	2	100.00
		TOTAL			36	38	94.74

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.29	99.59	93.16	99.06	100.00	97.81	95.49	95.94

Failure Buckets

• Offending '(curr_fwd | pend_req[d2h.d_source].pend)' has 2 failures:
  • Test rom_ctrl_sec_cm has 2 failures.

    • 0.rom_ctrl_sec_cm.24309307812064905260633118449746601306361931546214160749100828951804654662410
      Line 114, in log /nightly/current_run/scratch/master/rom_ctrl_32kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 292: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respSzEqReqSz_A: started at 30805188ps failed at 30805188ps
            Offending '(d2h.d_size === (curr_fwd ? curr_req.size : pend_req[d2h.d_source].size))'
        "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 293: tb.dut.rom_tlul_assert_device.gen_device.gen_d2h.respMustHaveReq_A: started at 30805188ps failed at 30805188ps
            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
      

    • 0.rom_ctrl_sec_cm.55574074009327119714889038397828062328255884698068059411593891988942526060884
      Line 676, in log /nightly/current_run/scratch/master/rom_ctrl_64kB-sim-vcs/0.rom_ctrl_sec_cm/latest/run.log

            Offending '(curr_fwd | pend_req[d2h.d_source].pend)'
        Starting assertion attempts at time 81374612ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_reqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:119))
        Starting assertion attempts at time 81374612ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_sramreqfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:120))
        Starting assertion attempts at time 81374612ps: level = 0 arg = tb.dut.u_tl_adapter_rom.u_rspfifo (from inst vcs_paramclassrepository (src/lowrisc_dv_rom_ctrl_env_0.1/seq_lib/rom_ctrl_common_vseq.sv:121))