RV_DM/USE_JTAG_INTERFACE Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke rv_dm_smoke 3.670s 1680.641us 1 1 100.00
V1 jtag_dtm_csr_hw_reset rv_dm_jtag_dtm_csr_hw_reset 0.950s 294.354us 1 1 100.00
V1 jtag_dtm_csr_rw rv_dm_jtag_dtm_csr_rw 0.960s 161.347us 1 1 100.00
V1 jtag_dtm_csr_bit_bash rv_dm_jtag_dtm_csr_bit_bash 3.710s 2585.815us 1 1 100.00
V1 jtag_dtm_csr_aliasing rv_dm_jtag_dtm_csr_aliasing 1.520s 501.096us 1 1 100.00
V1 jtag_dmi_csr_hw_reset rv_dm_jtag_dmi_csr_hw_reset 15.310s 9007.740us 1 1 100.00
V1 jtag_dmi_csr_rw rv_dm_jtag_dmi_csr_rw 2.880s 3903.675us 1 1 100.00
V1 jtag_dmi_csr_bit_bash rv_dm_jtag_dmi_csr_bit_bash 1.500s 2834.713us 1 1 100.00
V1 jtag_dmi_csr_aliasing rv_dm_jtag_dmi_csr_aliasing 22.130s 55141.154us 1 1 100.00
V1 jtag_dmi_cmderr_busy rv_dm_cmderr_busy 1.030s 389.887us 1 1 100.00
V1 jtag_dmi_cmderr_not_supported rv_dm_cmderr_not_supported 1.000s 129.184us 1 1 100.00
V1 cmderr_exception rv_dm_cmderr_exception 0.860s 173.803us 1 1 100.00
V1 mem_tl_access_resuming rv_dm_mem_tl_access_resuming 0.730s 107.658us 1 1 100.00
V1 mem_tl_access_halted rv_dm_mem_tl_access_halted 0.740s 113.546us 1 1 100.00
V1 cmderr_halt_resume rv_dm_cmderr_halt_resume 3.370s 1391.865us 1 1 100.00
V1 dataaddr_rw_access rv_dm_dataaddr_rw_access 0.770s 113.023us 1 1 100.00
V1 halt_resume rv_dm_halt_resume_whereto 0.860s 277.454us 1 1 100.00
V1 progbuf_busy rv_dm_cmderr_busy 1.030s 389.887us 1 1 100.00
V1 abstractcmd_status rv_dm_abstractcmd_status 1.160s 462.139us 1 1 100.00
V1 progbuf_read_write_execute rv_dm_progbuf_read_write_execute 0.710s 414.855us 1 1 100.00
V1 progbuf_exception rv_dm_cmderr_exception 0.860s 173.803us 1 1 100.00
V1 rom_read_access rv_dm_rom_read_access 0.770s 40.956us 1 1 100.00
V1 csr_hw_reset rv_dm_csr_hw_reset 1.910s 504.193us 1 1 100.00
V1 csr_rw rv_dm_csr_rw 1.260s 104.202us 1 1 100.00
V1 csr_bit_bash rv_dm_csr_bit_bash 38.560s 5945.040us 1 1 100.00
V1 csr_aliasing rv_dm_csr_aliasing 18.000s 2453.902us 1 1 100.00
V1 csr_mem_rw_with_rand_reset rv_dm_csr_mem_rw_with_rand_reset 0.780s 26.817us 0 1 0.00
V1 regwen_csr_and_corresponding_lockable_csr rv_dm_csr_aliasing 18.000s 2453.902us 1 1 100.00
rv_dm_csr_rw 1.260s 104.202us 1 1 100.00
V1 mem_walk rv_dm_mem_walk 0.720s 35.391us 1 1 100.00
V1 mem_partial_access rv_dm_mem_partial_access 0.670s 88.236us 1 1 100.00
V1 TOTAL 26 27 96.30
V2 idcode rv_dm_smoke 3.670s 1680.641us 1 1 100.00
V2 jtag_dtm_hard_reset rv_dm_jtag_dtm_hard_reset 1.250s 816.922us 1 1 100.00
V2 jtag_dtm_idle_hint rv_dm_jtag_dtm_idle_hint 0.960s 277.488us 1 1 100.00
V2 jtag_dmi_failed_op rv_dm_dmi_failed_op 0.900s 110.443us 1 1 100.00
V2 jtag_dmi_dm_inactive rv_dm_jtag_dmi_dm_inactive 1.040s 308.311us 1 1 100.00
V2 sba rv_dm_sba_tl_access 329.230s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 158.740s 300000.000us 0 1 0.00
V2 bad_sba rv_dm_bad_sba_tl_access 152.420s 300000.000us 0 1 0.00
V2 sba_autoincrement rv_dm_autoincr_sba_tl_access 549.060s 300000.000us 0 1 0.00
V2 jtag_dmi_debug_disabled rv_dm_jtag_dmi_debug_disabled 0.790s 128.285us 1 1 100.00
V2 sba_debug_disabled rv_dm_sba_debug_disabled 1.860s 680.237us 1 1 100.00
V2 ndmreset_req rv_dm_ndmreset_req 1.120s 769.170us 1 1 100.00
V2 hart_unavail rv_dm_hart_unavail 1.070s 359.252us 1 1 100.00
V2 tap_ctrl_transitions rv_dm_tap_fsm_rand_reset 0.920s 38.059us 0 1 0.00
rv_dm_tap_fsm 5.030s 4727.086us 1 1 100.00
V2 hartsel_warl rv_dm_hartsel_warl 0.730s 462.765us 1 1 100.00
V2 stress_all rv_dm_stress_all 8.030s 4140.934us 1 1 100.00
V2 alert_test rv_dm_alert_test 0.650s 80.890us 1 1 100.00
V2 tl_d_oob_addr_access rv_dm_tl_errors 0.830s 95.941us 0 1 0.00
V2 tl_d_illegal_access rv_dm_tl_errors 0.830s 95.941us 0 1 0.00
V2 tl_d_outstanding_access rv_dm_csr_aliasing 18.000s 2453.902us 1 1 100.00
rv_dm_csr_hw_reset 1.910s 504.193us 1 1 100.00
rv_dm_csr_rw 1.260s 104.202us 1 1 100.00
rv_dm_same_csr_outstanding 5.730s 823.423us 1 1 100.00
V2 tl_d_partial_access rv_dm_csr_aliasing 18.000s 2453.902us 1 1 100.00
rv_dm_csr_hw_reset 1.910s 504.193us 1 1 100.00
rv_dm_csr_rw 1.260s 104.202us 1 1 100.00
rv_dm_same_csr_outstanding 5.730s 823.423us 1 1 100.00
V2 TOTAL 13 19 68.42
V2S tl_intg_err rv_dm_tl_intg_err 14.280s 5768.511us 1 1 100.00
rv_dm_sec_cm 1.300s 766.250us 1 1 100.00
V2S sec_cm_bus_integrity rv_dm_tl_intg_err 14.280s 5768.511us 1 1 100.00
V2S sec_cm_lc_hw_debug_en_intersig_mubi rv_dm_sba_debug_disabled 1.860s 680.237us 1 1 100.00
rv_dm_debug_disabled 0.870s 105.386us 1 1 100.00
V2S sec_cm_lc_dft_en_intersig_mubi rv_dm_sba_debug_disabled 1.860s 680.237us 1 1 100.00
rv_dm_debug_disabled 0.870s 105.386us 1 1 100.00
V2S sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi rv_dm_smoke 3.670s 1680.641us 1 1 100.00
V2S sec_cm_dm_en_ctrl_lc_gated rv_dm_buffered_enable 1.190s 243.843us 1 1 100.00
V2S sec_cm_sba_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 0.830s 91.945us 1 1 100.00
V2S sec_cm_mem_tl_lc_gate_fsm_sparse rv_dm_sparse_lc_gate_fsm 0.830s 91.945us 1 1 100.00
V2S sec_cm_exec_ctrl_mubi rv_dm_buffered_enable 1.190s 243.843us 1 1 100.00
V2S TOTAL 5 5 100.00
V3 stress_all_with_rand_reset rv_dm_stress_all_with_rand_reset 0.990s 174.292us 0 1 0.00
V3 TOTAL 0 1 0.00
Unmapped tests rv_dm_scanmode 0.660s 33.757us 1 1 100.00
TOTAL 45 53 84.91

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
78.03 94.46 84.74 71.49 76.62 85.00 94.12 39.79

Failure Buckets