RV_TIMER Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	random	rv_timer_random	2.570s	1247.031us	1	1	100.00
V1	csr_hw_reset	rv_timer_csr_hw_reset	0.860s	27.097us	1	1	100.00
V1	csr_rw	rv_timer_csr_rw	0.730s	49.452us	1	1	100.00
V1	csr_bit_bash	rv_timer_csr_bit_bash	1.430s	39.120us	1	1	100.00
V1	csr_aliasing	rv_timer_csr_aliasing	0.710s	16.511us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	rv_timer_csr_mem_rw_with_rand_reset	1.410s	29.701us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	rv_timer_csr_rw	0.730s	49.452us	1	1	100.00
		rv_timer_csr_aliasing	0.710s	16.511us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	random_reset	rv_timer_random_reset	1.030s	460.171us	0	1	0.00
V2	disabled	rv_timer_disabled	2.130s	1437.344us	1	1	100.00
V2	cfg_update_on_fly	rv_timer_cfg_update_on_fly	46.090s	40399.948us	1	1	100.00
V2	no_interrupt_test	rv_timer_cfg_update_on_fly	46.090s	40399.948us	1	1	100.00
V2	stress	rv_timer_stress_all	2.020s	6950.608us	1	1	100.00
V2	alert_test	rv_timer_alert_test	0.610s	43.631us	1	1	100.00
V2	intr_test	rv_timer_intr_test	0.750s	35.529us	1	1	100.00
V2	tl_d_oob_addr_access	rv_timer_tl_errors	2.550s	46.211us	1	1	100.00
V2	tl_d_illegal_access	rv_timer_tl_errors	2.550s	46.211us	1	1	100.00
V2	tl_d_outstanding_access	rv_timer_csr_hw_reset	0.860s	27.097us	1	1	100.00
		rv_timer_csr_rw	0.730s	49.452us	1	1	100.00
		rv_timer_csr_aliasing	0.710s	16.511us	1	1	100.00
		rv_timer_same_csr_outstanding	0.970s	180.446us	1	1	100.00
V2	tl_d_partial_access	rv_timer_csr_hw_reset	0.860s	27.097us	1	1	100.00
		rv_timer_csr_rw	0.730s	49.452us	1	1	100.00
		rv_timer_csr_aliasing	0.710s	16.511us	1	1	100.00
		rv_timer_same_csr_outstanding	0.970s	180.446us	1	1	100.00
V2		TOTAL			7	8	87.50
V2S	tl_intg_err	rv_timer_tl_intg_err	0.960s	84.775us	1	1	100.00
		rv_timer_sec_cm	0.970s	69.847us	1	1	100.00
V2S	sec_cm_bus_integrity	rv_timer_tl_intg_err	0.960s	84.775us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	min_value	rv_timer_min	1.190s	758.203us	0	1	0.00
V3	max_value	rv_timer_max	0.750s	185.892us	0	1	0.00
V3	stress_all_with_rand_reset	rv_timer_stress_all_with_rand_reset	15.110s	4232.791us	1	1	100.00
V3		TOTAL			1	3	33.33
		TOTAL			16	19	84.21

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
98.73	100.00	100.00	100.00	--	100.00	96.82	95.59

Failure Buckets

• UVM_FATAL (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state* (addr=*) == * has 2 failures:

  • Test rv_timer_min has 1 failures.

    • 0.rv_timer_min.35131769952819889103383045506543166906302352451717340192639020193259372205306
      Line 74, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_min/latest/run.log

        UVM_FATAL @ 758203252 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x6e663d04) == 0x1
        UVM_INFO @ 758203252 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rv_timer_random_reset has 1 failures.

    • 0.rv_timer_random_reset.97807591296669322010057921471572221791333487814659192627483679244738155603093
      Line 73, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_random_reset/latest/run.log

        UVM_FATAL @ 460170792 ps: (rv_timer_base_vseq.sv:163) [intr_state_spinwait] timeout rv_timer_reg_block.intr_state0 (addr=0x5fd2ab04) == 0x1
        UVM_INFO @ 460170792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (rv_timer_scoreboard.sv:250) [scoreboard] Check failed csr.get_mirrored_value() == item.d_data (* [*] vs * [*]) has 1 failures:

  • Test rv_timer_max has 1 failures.

    • 0.rv_timer_max.33098024237005272464918214939319958348801684489120996065804936345251578681392
      Line 72, in log /nightly/current_run/scratch/master/rv_timer-sim-vcs/0.rv_timer_max/latest/run.log

        UVM_ERROR @ 185892124 ps: (rv_timer_scoreboard.sv:250) [uvm_test_top.env.scoreboard] Check failed csr.get_mirrored_value() == item.d_data (1 [0x1] vs 0 [0x0])
        UVM_INFO @ 185892124 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---