SPI_DEVICE/1R1W Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_device_flash_and_tpm	121.230s	213460.343us	2	2	100.00
V1	csr_hw_reset	spi_device_csr_hw_reset	1.180s	165.039us	2	2	100.00
V1	csr_rw	spi_device_csr_rw	1.600s	98.474us	2	2	100.00
V1	csr_bit_bash	spi_device_csr_bit_bash	22.450s	1025.356us	2	2	100.00
V1	csr_aliasing	spi_device_csr_aliasing	16.500s	1133.710us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	spi_device_csr_mem_rw_with_rand_reset	2.050s	107.401us	2	2	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_device_csr_rw	1.600s	98.474us	2	2	100.00
		spi_device_csr_aliasing	16.500s	1133.710us	2	2	100.00
V1	mem_walk	spi_device_mem_walk	0.810s	30.215us	2	2	100.00
V1	mem_partial_access	spi_device_mem_partial_access	1.890s	220.041us	2	2	100.00
V1		TOTAL			16	16	100.00
V2	csb_read	spi_device_csb_read	0.790s	18.095us	2	2	100.00
V2	mem_parity	spi_device_mem_parity	0.980s	18.120us	1	2	50.00
V2	mem_cfg	spi_device_ram_cfg	0.770s	38.735us	1	2	50.00
V2	tpm_read	spi_device_tpm_rw	0.970s	40.719us	2	2	100.00
V2	tpm_write	spi_device_tpm_rw	0.970s	40.719us	2	2	100.00
V2	tpm_hw_reg	spi_device_tpm_read_hw_reg	4.370s	4341.972us	2	2	100.00
		spi_device_tpm_sts_read	0.970s	110.629us	2	2	100.00
V2	tpm_fully_random_case	spi_device_tpm_all	18.090s	4055.630us	2	2	100.00
V2	pass_cmd_filtering	spi_device_pass_cmd_filtering	4.410s	1071.634us	2	2	100.00
		spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	pass_addr_translation	spi_device_pass_addr_payload_swap	2.530s	159.134us	2	2	100.00
		spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	pass_payload_translation	spi_device_pass_addr_payload_swap	2.530s	159.134us	2	2	100.00
		spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	cmd_info_slots	spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	cmd_read_status	spi_device_intercept	10.060s	1585.221us	2	2	100.00
		spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	cmd_read_jedec	spi_device_intercept	10.060s	1585.221us	2	2	100.00
		spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	cmd_read_sfdp	spi_device_intercept	10.060s	1585.221us	2	2	100.00
		spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	cmd_fast_read	spi_device_intercept	10.060s	1585.221us	2	2	100.00
		spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	cmd_read_pipeline	spi_device_intercept	10.060s	1585.221us	2	2	100.00
		spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	flash_cmd_upload	spi_device_upload	17.060s	15744.439us	2	2	100.00
V2	mailbox_command	spi_device_mailbox	13.070s	10189.656us	2	2	100.00
V2	mailbox_cross_outside_command	spi_device_mailbox	13.070s	10189.656us	2	2	100.00
V2	mailbox_cross_inside_command	spi_device_mailbox	13.070s	10189.656us	2	2	100.00
V2	cmd_read_buffer	spi_device_flash_mode	9.830s	2424.261us	2	2	100.00
		spi_device_read_buffer_direct	7.620s	688.228us	2	2	100.00
V2	cmd_dummy_cycle	spi_device_mailbox	13.070s	10189.656us	2	2	100.00
		spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	quad_spi	spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	dual_spi	spi_device_flash_all	125.040s	222790.610us	2	2	100.00
V2	4b_3b_feature	spi_device_cfg_cmd	5.460s	1576.622us	2	2	100.00
V2	write_enable_disable	spi_device_cfg_cmd	5.460s	1576.622us	2	2	100.00
V2	TPM_with_flash_or_passthrough_mode	spi_device_flash_and_tpm	121.230s	213460.343us	2	2	100.00
V2	tpm_and_flash_trans_with_min_inactive_time	spi_device_flash_and_tpm_min_idle	103.050s	36884.491us	2	2	100.00
V2	stress_all	spi_device_stress_all	54.580s	5709.702us	2	2	100.00
V2	alert_test	spi_device_alert_test	0.860s	10.828us	2	2	100.00
V2	intr_test	spi_device_intr_test	0.840s	20.715us	2	2	100.00
V2	tl_d_oob_addr_access	spi_device_tl_errors	3.830s	521.506us	2	2	100.00
V2	tl_d_illegal_access	spi_device_tl_errors	3.830s	521.506us	2	2	100.00
V2	tl_d_outstanding_access	spi_device_csr_hw_reset	1.180s	165.039us	2	2	100.00
		spi_device_csr_rw	1.600s	98.474us	2	2	100.00
		spi_device_csr_aliasing	16.500s	1133.710us	2	2	100.00
		spi_device_same_csr_outstanding	2.110s	46.424us	2	2	100.00
V2	tl_d_partial_access	spi_device_csr_hw_reset	1.180s	165.039us	2	2	100.00
		spi_device_csr_rw	1.600s	98.474us	2	2	100.00
		spi_device_csr_aliasing	16.500s	1133.710us	2	2	100.00
		spi_device_same_csr_outstanding	2.110s	46.424us	2	2	100.00
V2		TOTAL			42	44	95.45
V2S	tl_intg_err	spi_device_tl_intg_err	10.740s	568.445us	2	2	100.00
		spi_device_sec_cm	1.260s	1203.523us	2	2	100.00
V2S	sec_cm_bus_integrity	spi_device_tl_intg_err	10.740s	568.445us	2	2	100.00
V2S		TOTAL			4	4	100.00
	Unmapped tests	spi_device_flash_mode_ignore_cmds	153.670s	40666.300us	2	2	100.00
		TOTAL			64	66	96.97

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
89.77	99.10	96.38	83.54	89.36	98.39	94.30	67.36

Failure Buckets

• UVM_ERROR (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[*]) has 1 failures:

  • Test spi_device_mem_parity has 1 failures.

    • 0.spi_device_mem_parity.55784722840784123996370235470915928622959607209077028238252853090979764639250
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_mem_parity/latest/run.log

        UVM_ERROR @   2252048 ps: (uvm_hdl_vcs.c:1035) [UVM/DPI/HDL_SET] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[86])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
        UVM_ERROR @   2252048 ps: (spi_device_mem_parity_vseq.sv:44) [uvm_test_top.env.virtual_sequencer.spi_device_mem_parity_vseq] Check failed (uvm_hdl_read(egress_path, mem_data))
        UVM_ERROR @   2252048 ps: (uvm_hdl_vcs.c:1185) [UVM/DPI/HDL_DEPOSIT] set: unable to locate hdl path (tb.dut.u_spid_dpram.gen_ram2p.u_memory_2p.u_mem.mem[982])
         Either the name is incorrect, or you may not have PLI/ACC visibility to that name
      

• UVM_ERROR (spi_device_ram_cfg_vseq.sv:27) [spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (* [*] vs * [*]) has 1 failures:

  • Test spi_device_ram_cfg has 1 failures.

    • 0.spi_device_ram_cfg.101010369853970094889867560131888545653216265978471554521980612829177511009141
      Line 73, in log /nightly/current_run/scratch/master/spi_device_1r1w-sim-vcs/0.spi_device_ram_cfg/latest/run.log

        UVM_ERROR @    860142 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x591a80 [10110010001101010000000] vs 0x0 [0])
        UVM_ERROR @    918142 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x6bbb14 [11010111011101100010100] vs 0x0 [0])
        UVM_ERROR @    959142 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x937d05 [100100110111110100000101] vs 0x0 [0])
        UVM_ERROR @    990142 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0xf9f7c5 [111110011111011111000101] vs 0x0 [0])
        UVM_ERROR @   1031142 ps: (spi_device_ram_cfg_vseq.sv:27) [uvm_test_top.env.virtual_sequencer.spi_device_ram_cfg_vseq] Check failed src_ram_cfg === egress_ram_cfg (0x5aafdc [10110101010111111011100] vs 0x0 [0])