SPI_HOST Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: XCELIUM

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	spi_host_smoke	10.000s	800.622us	1	1	100.00
V1	csr_hw_reset	spi_host_csr_hw_reset	1.000s	158.491us	1	1	100.00
V1	csr_rw	spi_host_csr_rw	1.000s	36.874us	1	1	100.00
V1	csr_bit_bash	spi_host_csr_bit_bash	3.000s	55.893us	1	1	100.00
V1	csr_aliasing	spi_host_csr_aliasing	1.000s	18.059us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	spi_host_csr_mem_rw_with_rand_reset	2.000s	89.654us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	spi_host_csr_rw	1.000s	36.874us	1	1	100.00
		spi_host_csr_aliasing	1.000s	18.059us	1	1	100.00
V1	mem_walk	spi_host_mem_walk	1.000s	32.584us	1	1	100.00
V1	mem_partial_access	spi_host_mem_partial_access	2.000s	17.841us	1	1	100.00
V1		TOTAL			8	8	100.00
V2	performance	spi_host_performance	1.000s	24.873us	1	1	100.00
V2	error_event_intr	spi_host_overflow_underflow	3.000s	425.993us	1	1	100.00
		spi_host_error_cmd	2.000s	37.428us	1	1	100.00
		spi_host_event	42.000s	1550.254us	1	1	100.00
V2	clock_rate	spi_host_speed	3.000s	100.271us	1	1	100.00
V2	speed	spi_host_speed	3.000s	100.271us	1	1	100.00
V2	chip_select_timing	spi_host_speed	3.000s	100.271us	1	1	100.00
V2	sw_reset	spi_host_sw_reset	4.000s	126.924us	1	1	100.00
V2	passthrough_mode	spi_host_passthrough_mode	1.000s	27.042us	1	1	100.00
V2	cpol_cpha	spi_host_speed	3.000s	100.271us	1	1	100.00
V2	full_cycle	spi_host_speed	3.000s	100.271us	1	1	100.00
V2	duplex	spi_host_smoke	10.000s	800.622us	1	1	100.00
V2	tx_rx_only	spi_host_smoke	10.000s	800.622us	1	1	100.00
V2	stress_all	spi_host_stress_all	8.000s	570.953us	1	1	100.00
V2	spien	spi_host_spien	19.000s	10393.605us	0	1	0.00
V2	stall	spi_host_status_stall	35.000s	2950.265us	1	1	100.00
V2	Idlecsbactive	spi_host_idlecsbactive	4.000s	279.561us	1	1	100.00
V2	data_fifo_status	spi_host_overflow_underflow	3.000s	425.993us	1	1	100.00
V2	alert_test	spi_host_alert_test	2.000s	17.737us	1	1	100.00
V2	intr_test	spi_host_intr_test	2.000s	17.951us	1	1	100.00
V2	tl_d_oob_addr_access	spi_host_tl_errors	3.000s	264.185us	1	1	100.00
V2	tl_d_illegal_access	spi_host_tl_errors	3.000s	264.185us	1	1	100.00
V2	tl_d_outstanding_access	spi_host_csr_hw_reset	1.000s	158.491us	1	1	100.00
		spi_host_csr_rw	1.000s	36.874us	1	1	100.00
		spi_host_csr_aliasing	1.000s	18.059us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	98.215us	1	1	100.00
V2	tl_d_partial_access	spi_host_csr_hw_reset	1.000s	158.491us	1	1	100.00
		spi_host_csr_rw	1.000s	36.874us	1	1	100.00
		spi_host_csr_aliasing	1.000s	18.059us	1	1	100.00
		spi_host_same_csr_outstanding	2.000s	98.215us	1	1	100.00
V2		TOTAL			14	15	93.33
V2S	tl_intg_err	spi_host_sec_cm	1.000s	72.644us	1	1	100.00
		spi_host_tl_intg_err	1.000s	56.737us	1	1	100.00
V2S	sec_cm_bus_integrity	spi_host_tl_intg_err	1.000s	56.737us	1	1	100.00
V2S		TOTAL			2	2	100.00
	Unmapped tests	spi_host_upper_range_clkdiv	328.000s	10842.035us	1	1	100.00
		TOTAL			25	26	96.15

Coverage Results

Coverage Dashboard

Score	Block	Branch	Statement	Expression	Toggle	Fsm	Assertion	CoverGroup
95.75	96.78	93.25	98.58	92.09	88.02	100.00	95.21	86.67

Failure Buckets

• UVM_FATAL (spi_host_base_vseq.sv:237) virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = *ns spi_host_reg_block.status.rxqd (addr=*, Comparison=CompareOpEq, exp_data=*, call_count=* has 1 failures:
  • Test spi_host_spien has 1 failures.

    • 0.spi_host_spien.73965199900327818922821795317887064551033905851720155581121305892536046524627
      Line 276, in log /nightly/current_run/scratch/master/spi_host-sim-xcelium/0.spi_host_spien/latest/run.log

        UVM_FATAL @ 10393604637 ps: (spi_host_base_vseq.sv:237) uvm_test_top.env.virtual_sequencer [spi_host_env_pkg::spi_host_base_vseq.stoppable_timeout()] timeout = 10000000ns spi_host_reg_block.status.rxqd (addr=0x220aa994, Comparison=CompareOpEq, exp_data=0x0, call_count=42
        UVM_INFO @ 10393604637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---