SRAM_CTRL/MAIN Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sram_ctrl_smoke	16.640s	421.799us	2	2	100.00
V1	csr_hw_reset	sram_ctrl_csr_hw_reset	0.990s	47.972us	2	2	100.00
V1	csr_rw	sram_ctrl_csr_rw	0.990s	42.056us	2	2	100.00
V1	csr_bit_bash	sram_ctrl_csr_bit_bash	1.960s	490.978us	2	2	100.00
V1	csr_aliasing	sram_ctrl_csr_aliasing	1.060s	18.282us	2	2	100.00
V1	csr_mem_rw_with_rand_reset	sram_ctrl_csr_mem_rw_with_rand_reset	2.820s	1426.639us	1	2	50.00
V1	regwen_csr_and_corresponding_lockable_csr	sram_ctrl_csr_rw	0.990s	42.056us	2	2	100.00
		sram_ctrl_csr_aliasing	1.060s	18.282us	2	2	100.00
V1	mem_walk	sram_ctrl_mem_walk	264.970s	224649.685us	2	2	100.00
V1	mem_partial_access	sram_ctrl_mem_partial_access	72.070s	6042.997us	2	2	100.00
V1		TOTAL			15	16	93.75
V2	multiple_keys	sram_ctrl_multiple_keys	322.180s	32651.865us	2	2	100.00
V2	stress_pipeline	sram_ctrl_stress_pipeline	187.990s	4482.682us	2	2	100.00
V2	bijection	sram_ctrl_bijection	1235.310s	248231.328us	2	2	100.00
V2	access_during_key_req	sram_ctrl_access_during_key_req	281.810s	14784.560us	2	2	100.00
V2	lc_escalation	sram_ctrl_lc_escalation	23.430s	5573.566us	2	2	100.00
V2	executable	sram_ctrl_executable	820.420s	32911.101us	2	2	100.00
V2	partial_access	sram_ctrl_partial_access	11.290s	253.549us	2	2	100.00
		sram_ctrl_partial_access_b2b	317.940s	185387.035us	2	2	100.00
V2	max_throughput	sram_ctrl_max_throughput	28.670s	209.620us	2	2	100.00
		sram_ctrl_throughput_w_partial_write	49.190s	805.042us	2	2	100.00
		sram_ctrl_throughput_w_readback	13.530s	960.233us	2	2	100.00
V2	regwen	sram_ctrl_regwen	268.340s	2319.342us	2	2	100.00
V2	ram_cfg	sram_ctrl_ram_cfg	4.460s	1403.213us	2	2	100.00
V2	stress_all	sram_ctrl_stress_all	3452.960s	558862.244us	2	2	100.00
V2	alert_test	sram_ctrl_alert_test	0.930s	13.910us	2	2	100.00
V2	tl_d_oob_addr_access	sram_ctrl_tl_errors	3.690s	91.601us	2	2	100.00
V2	tl_d_illegal_access	sram_ctrl_tl_errors	3.690s	91.601us	2	2	100.00
V2	tl_d_outstanding_access	sram_ctrl_csr_hw_reset	0.990s	47.972us	2	2	100.00
		sram_ctrl_csr_rw	0.990s	42.056us	2	2	100.00
		sram_ctrl_csr_aliasing	1.060s	18.282us	2	2	100.00
		sram_ctrl_same_csr_outstanding	1.170s	50.229us	2	2	100.00
V2	tl_d_partial_access	sram_ctrl_csr_hw_reset	0.990s	47.972us	2	2	100.00
		sram_ctrl_csr_rw	0.990s	42.056us	2	2	100.00
		sram_ctrl_csr_aliasing	1.060s	18.282us	2	2	100.00
		sram_ctrl_same_csr_outstanding	1.170s	50.229us	2	2	100.00
V2		TOTAL			34	34	100.00
V2S	passthru_mem_tl_intg_err	sram_ctrl_passthru_mem_tl_intg_err	37.240s	7143.844us	2	2	100.00
V2S	tl_intg_err	sram_ctrl_tl_intg_err	2.950s	427.162us	2	2	100.00
		sram_ctrl_sec_cm	1.000s	42.076us	0	2	0.00
V2S	prim_count_check	sram_ctrl_sec_cm	1.000s	42.076us	0	2	0.00
V2S	sec_cm_bus_integrity	sram_ctrl_tl_intg_err	2.950s	427.162us	2	2	100.00
V2S	sec_cm_ctrl_config_regwen	sram_ctrl_regwen	268.340s	2319.342us	2	2	100.00
V2S	sec_cm_readback_config_regwen	sram_ctrl_regwen	268.340s	2319.342us	2	2	100.00
V2S	sec_cm_exec_config_regwen	sram_ctrl_csr_rw	0.990s	42.056us	2	2	100.00
V2S	sec_cm_exec_config_mubi	sram_ctrl_executable	820.420s	32911.101us	2	2	100.00
V2S	sec_cm_exec_intersig_mubi	sram_ctrl_executable	820.420s	32911.101us	2	2	100.00
V2S	sec_cm_lc_hw_debug_en_intersig_mubi	sram_ctrl_executable	820.420s	32911.101us	2	2	100.00
V2S	sec_cm_lc_escalate_en_intersig_mubi	sram_ctrl_lc_escalation	23.430s	5573.566us	2	2	100.00
V2S	sec_cm_prim_ram_ctrl_mubi	sram_ctrl_mubi_enc_err	7.680s	2714.766us	2	2	100.00
V2S	sec_cm_mem_integrity	sram_ctrl_passthru_mem_tl_intg_err	37.240s	7143.844us	2	2	100.00
V2S	sec_cm_mem_readback	sram_ctrl_readback_err	8.710s	3670.022us	2	2	100.00
V2S	sec_cm_mem_scramble	sram_ctrl_smoke	16.640s	421.799us	2	2	100.00
V2S	sec_cm_addr_scramble	sram_ctrl_smoke	16.640s	421.799us	2	2	100.00
V2S	sec_cm_instr_bus_lc_gated	sram_ctrl_executable	820.420s	32911.101us	2	2	100.00
V2S	sec_cm_ram_tl_lc_gate_fsm_sparse	sram_ctrl_sec_cm	1.000s	42.076us	0	2	0.00
V2S	sec_cm_key_global_esc	sram_ctrl_lc_escalation	23.430s	5573.566us	2	2	100.00
V2S	sec_cm_key_local_esc	sram_ctrl_sec_cm	1.000s	42.076us	0	2	0.00
V2S	sec_cm_init_ctr_redun	sram_ctrl_sec_cm	1.000s	42.076us	0	2	0.00
V2S	sec_cm_scramble_key_sideload	sram_ctrl_smoke	16.640s	421.799us	2	2	100.00
V2S	sec_cm_tlul_fifo_ctr_redun	sram_ctrl_sec_cm	1.000s	42.076us	0	2	0.00
V2S		TOTAL			8	10	80.00
V3	stress_all_with_rand_reset	sram_ctrl_stress_all_with_rand_reset	135.810s	8873.790us	2	2	100.00
V3		TOTAL			2	2	100.00
		TOTAL			59	62	95.16

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
94.05	98.57	92.17	90.71	90.48	96.53	95.83	94.06

Failure Buckets

• Offending '(!$isunknown(rdata_o))' has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.85298579051153352897708015655771327450828976805786935746134897911927074213714
      Line 99, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

            Offending '(!$isunknown(rdata_o))'
        UVM_ERROR @  42075973 ps: (prim_fifo_sync.sv:224) [ASSERT FAILED] DataKnown_A
        UVM_INFO @  42075973 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: * has 1 failures:

  • Test sram_ctrl_csr_mem_rw_with_rand_reset has 1 failures.

    • 0.sram_ctrl_csr_mem_rw_with_rand_reset.78303014231103713283785331553361498917826574640154712729315965670725832682493
      Line 95, in log /nightly/current_run/scratch/master/sram_ctrl_ret-sim-vcs/0.sram_ctrl_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 286094676 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (4 [0x4] vs 9 [0x9]) Regname: sram_ctrl_regs_reg_block.scr_key_rotated reset value: 0x9
        UVM_INFO @ 286094676 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_*] Check failed obs == exp (* [*] vs * [*]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: * has 1 failures:

  • Test sram_ctrl_sec_cm has 1 failures.

    • 0.sram_ctrl_sec_cm.80503335996203083476680163324744834729207505248061563702971997918276973707471
      Line 97, in log /nightly/current_run/scratch/master/sram_ctrl_main-sim-vcs/0.sram_ctrl_sec_cm/latest/run.log

        UVM_ERROR @   6210006 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: sram_ctrl_regs_reg_block.status.init_error reset value: 0x0
        UVM_INFO @   6210006 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---