SYSRST_CTRL Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	sysrst_ctrl_smoke	1.290s	2145.516us	1	1	100.00
V1	input_output_inverted	sysrst_ctrl_in_out_inverted	1.800s	2477.878us	1	1	100.00
V1	combo_detect_ec_rst	sysrst_ctrl_combo_detect_ec_rst	1.230s	2287.492us	1	1	100.00
V1	combo_detect_ec_rst_with_pre_cond	sysrst_ctrl_combo_detect_ec_rst_with_pre_cond	5.520s	2534.525us	1	1	100.00
V1	csr_hw_reset	sysrst_ctrl_csr_hw_reset	2.120s	6121.953us	1	1	100.00
V1	csr_rw	sysrst_ctrl_csr_rw	5.120s	2061.456us	1	1	100.00
V1	csr_bit_bash	sysrst_ctrl_csr_bit_bash	126.440s	69555.073us	1	1	100.00
V1	csr_aliasing	sysrst_ctrl_csr_aliasing	8.630s	2721.790us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	sysrst_ctrl_csr_mem_rw_with_rand_reset	4.880s	2037.825us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	sysrst_ctrl_csr_rw	5.120s	2061.456us	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.630s	2721.790us	1	1	100.00
V1		TOTAL			9	9	100.00
V2	combo_detect	sysrst_ctrl_combo_detect	42.020s	87150.088us	1	1	100.00
V2	combo_detect_with_pre_cond	sysrst_ctrl_combo_detect_with_pre_cond	88.230s	164804.060us	1	1	100.00
V2	auto_block_key_outputs	sysrst_ctrl_auto_blk_key_output	48.940s	50300.108us	1	1	100.00
V2	keyboard_input_triggered_interrupt	sysrst_ctrl_edge_detect	2.410s	4372.964us	1	1	100.00
V2	pin_output_keyboard_inversion_control	sysrst_ctrl_pin_override_test	1.800s	2525.773us	1	1	100.00
V2	pin_input_value_accessibility	sysrst_ctrl_pin_access_test	1.650s	2180.064us	1	1	100.00
V2	ec_power_on_reset	sysrst_ctrl_ec_pwr_on_rst	1.430s	3295.503us	1	1	100.00
V2	flash_write_protect_output	sysrst_ctrl_flash_wr_prot_out	2.960s	2622.033us	1	1	100.00
V2	ultra_low_power_test	sysrst_ctrl_ultra_low_pwr	1.760s	6169.205us	1	1	100.00
V2	sysrst_ctrl_feature_disable	sysrst_ctrl_feature_disable	68.690s	39307.701us	1	1	100.00
V2	stress_all	sysrst_ctrl_stress_all	22.190s	12201.827us	1	1	100.00
V2	alert_test	sysrst_ctrl_alert_test	4.100s	2013.749us	1	1	100.00
V2	intr_test	sysrst_ctrl_intr_test	3.250s	2015.478us	1	1	100.00
V2	tl_d_oob_addr_access	sysrst_ctrl_tl_errors	5.780s	2106.563us	1	1	100.00
V2	tl_d_illegal_access	sysrst_ctrl_tl_errors	5.780s	2106.563us	1	1	100.00
V2	tl_d_outstanding_access	sysrst_ctrl_csr_hw_reset	2.120s	6121.953us	1	1	100.00
		sysrst_ctrl_csr_rw	5.120s	2061.456us	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.630s	2721.790us	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	6.270s	10003.664us	1	1	100.00
V2	tl_d_partial_access	sysrst_ctrl_csr_hw_reset	2.120s	6121.953us	1	1	100.00
		sysrst_ctrl_csr_rw	5.120s	2061.456us	1	1	100.00
		sysrst_ctrl_csr_aliasing	8.630s	2721.790us	1	1	100.00
		sysrst_ctrl_same_csr_outstanding	6.270s	10003.664us	1	1	100.00
V2		TOTAL			15	15	100.00
V2S	tl_intg_err	sysrst_ctrl_sec_cm	34.740s	42027.882us	1	1	100.00
		sysrst_ctrl_tl_intg_err	11.620s	22573.145us	1	1	100.00
V2S	sec_cm_bus_integrity	sysrst_ctrl_tl_intg_err	11.620s	22573.145us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	sysrst_ctrl_stress_all_with_rand_reset	12.550s	6534.578us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			27	27	100.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
85.54	95.22	93.21	100.00	60.90	96.07	87.93	65.45