UART Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: 846e611

Branch: master

Testplan

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	uart_smoke	1.550s	452.323us	1	1	100.00
V1	csr_hw_reset	uart_csr_hw_reset	0.680s	45.166us	1	1	100.00
V1	csr_rw	uart_csr_rw	0.660s	61.075us	1	1	100.00
V1	csr_bit_bash	uart_csr_bit_bash	1.630s	467.724us	1	1	100.00
V1	csr_aliasing	uart_csr_aliasing	0.980s	29.169us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	uart_csr_mem_rw_with_rand_reset	0.850s	39.513us	1	1	100.00
V1	regwen_csr_and_corresponding_lockable_csr	uart_csr_rw	0.660s	61.075us	1	1	100.00
		uart_csr_aliasing	0.980s	29.169us	1	1	100.00
V1		TOTAL			6	6	100.00
V2	base_random_seq	uart_tx_rx	3.310s	6958.851us	1	1	100.00
V2	parity	uart_smoke	1.550s	452.323us	1	1	100.00
		uart_tx_rx	3.310s	6958.851us	1	1	100.00
V2	parity_error	uart_intr	15.450s	44072.597us	1	1	100.00
		uart_rx_parity_err	36.460s	21531.479us	1	1	100.00
V2	watermark	uart_tx_rx	3.310s	6958.851us	1	1	100.00
		uart_intr	15.450s	44072.597us	1	1	100.00
V2	fifo_full	uart_fifo_full	17.940s	56119.609us	1	1	100.00
V2	fifo_overflow	uart_fifo_overflow	44.430s	30718.108us	1	1	100.00
V2	fifo_reset	uart_fifo_reset	178.160s	51800.646us	1	1	100.00
V2	rx_frame_err	uart_intr	15.450s	44072.597us	1	1	100.00
V2	rx_break_err	uart_intr	15.450s	44072.597us	1	1	100.00
V2	rx_timeout	uart_intr	15.450s	44072.597us	1	1	100.00
V2	perf	uart_perf	64.780s	19076.439us	1	1	100.00
V2	sys_loopback	uart_loopback	5.050s	4194.649us	1	1	100.00
V2	line_loopback	uart_loopback	5.050s	4194.649us	1	1	100.00
V2	rx_noise_filter	uart_noise_filter	6.690s	5623.764us	0	1	0.00
V2	rx_start_bit_filter	uart_rx_start_bit_filter	5.280s	4261.946us	1	1	100.00
V2	tx_overide	uart_tx_ovrd	8.470s	7697.510us	1	1	100.00
V2	rx_oversample	uart_rx_oversample	8.020s	4705.194us	1	1	100.00
V2	long_b2b_transfer	uart_long_xfer_wo_dly	507.670s	79173.948us	1	1	100.00
V2	stress_all	uart_stress_all	754.820s	193553.268us	1	1	100.00
V2	alert_test	uart_alert_test	0.850s	11.985us	1	1	100.00
V2	intr_test	uart_intr_test	0.810s	16.202us	1	1	100.00
V2	tl_d_oob_addr_access	uart_tl_errors	1.290s	38.284us	1	1	100.00
V2	tl_d_illegal_access	uart_tl_errors	1.290s	38.284us	1	1	100.00
V2	tl_d_outstanding_access	uart_csr_hw_reset	0.680s	45.166us	1	1	100.00
		uart_csr_rw	0.660s	61.075us	1	1	100.00
		uart_csr_aliasing	0.980s	29.169us	1	1	100.00
		uart_same_csr_outstanding	0.710s	71.109us	1	1	100.00
V2	tl_d_partial_access	uart_csr_hw_reset	0.680s	45.166us	1	1	100.00
		uart_csr_rw	0.660s	61.075us	1	1	100.00
		uart_csr_aliasing	0.980s	29.169us	1	1	100.00
		uart_same_csr_outstanding	0.710s	71.109us	1	1	100.00
V2		TOTAL			17	18	94.44
V2S	tl_intg_err	uart_sec_cm	0.980s	39.335us	1	1	100.00
		uart_tl_intg_err	1.330s	79.496us	1	1	100.00
V2S	sec_cm_bus_integrity	uart_tl_intg_err	1.330s	79.496us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	stress_all_with_rand_reset	uart_stress_all_with_rand_reset	16.440s	7758.567us	1	1	100.00
V3		TOTAL			1	1	100.00
		TOTAL			26	27	96.30

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
90.20	99.48	97.78	91.55	--	98.14	97.12	57.11

Failure Buckets

• UVM_ERROR (uart_scoreboard.sv:393) [scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (* [*] vs * [*]) check rx_idle fail: rx_en = *, uart_rx_clk_pulses = * has 1 failures:
  • Test uart_noise_filter has 1 failures.

    • 0.uart_noise_filter.19247182150093282010673976474152447008023524645481802608789126342014115967580
      Line 71, in log /nightly/current_run/scratch/master/uart-sim-vcs/0.uart_noise_filter/latest/run.log

        UVM_ERROR @  11963828 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  55363828 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @  55363828 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1
        UVM_ERROR @ 1242033828 ps: (uart_scoreboard.sv:393) [uvm_test_top.env.scoreboard] Check failed get_field_val(ral.status.rxidle, item.d_data) == rx_idle_exp (0 [0x0] vs 1 [0x1]) check rx_idle fail: rx_en = 1, uart_rx_clk_pulses = 0
        UVM_ERROR @ 1242033828 ps: (csr_utils_pkg.sv:456) [csr_utils_pkg::csr_rd_check.isolation_fork.unnamed$$_0] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: uart_reg_block.status.rxidle reset value: 0x1