CHIP Simulation Results

Monday November 17 2025 17:01:03 UTC

GitHub Revision: `846e611`

Branch: master

Simulator: VCS

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	139.940s	3479.718us	1	1	100.00
		chip_sw_example_rom	79.080s	2534.436us	1	1	100.00
		chip_sw_example_manufacturer	142.840s	2603.545us	1	1	100.00
		chip_sw_example_concurrency	114.000s	2323.117us	1	1	100.00
V1	csr_hw_reset	chip_csr_hw_reset	149.170s	5555.964us	1	1	100.00
V1	csr_rw	chip_csr_rw	324.090s	5680.326us	1	1	100.00
V1	csr_bit_bash	chip_csr_bit_bash	266.780s	4943.820us	1	1	100.00
V1	csr_aliasing	chip_csr_aliasing	5031.230s	40831.132us	1	1	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	41.350s	1981.577us	0	1	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	5031.230s	40831.132us	1	1	100.00
		chip_csr_rw	324.090s	5680.326us	1	1	100.00
V1	xbar_smoke	xbar_smoke	4.920s	120.456us	1	1	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	245.540s	4460.537us	1	1	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	245.540s	4460.537us	1	1	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	245.540s	4460.537us	1	1	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	368.020s	4137.276us	1	1	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	368.020s	4137.276us	1	1	100.00
		chip_sw_uart_tx_rx_idx1	365.880s	4326.677us	1	1	100.00
		chip_sw_uart_tx_rx_idx2	364.910s	4437.903us	1	1	100.00
		chip_sw_uart_tx_rx_idx3	428.880s	4618.443us	1	1	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1098.800s	8635.009us	1	1	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1052.300s	8451.392us	1	1	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	604.180s	8086.822us	1	1	100.00
V1		TOTAL			17	18	94.44
V2	chip_pin_mux	chip_padctrl_attributes	208.480s	5923.848us	1	1	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	208.480s	5923.848us	1	1	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	189.190s	3652.418us	1	1	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	147.530s	2667.817us	1	1	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	245.640s	4278.665us	1	1	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	90.650s	3089.747us	1	1	100.00
		chip_tap_straps_testunlock0	322.560s	6209.614us	1	1	100.00
		chip_tap_straps_rma	206.030s	4871.594us	1	1	100.00
		chip_tap_straps_prod	109.780s	3030.175us	1	1	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	142.660s	2857.626us	1	1	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	816.840s	9355.262us	1	1	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	362.640s	4919.027us	1	1	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	362.640s	4919.027us	1	1	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	536.330s	6960.285us	1	1	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs	2448.780s	23519.954us	0	1	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	321.010s	4671.559us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	596.280s	5781.991us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3428.800s	19151.090us	1	1	100.00
		chip_sw_aes_enc_jitter_en	198.560s	2799.012us	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	779.340s	6640.829us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	134.660s	2512.085us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1191.760s	10344.138us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	206.340s	3200.939us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	361.410s	4225.301us	1	1	100.00
		chip_sw_clkmgr_jitter	144.710s	3369.148us	1	1	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	191.040s	3659.512us	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	625.300s	8384.948us	1	1	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	243.690s	4782.185us	1	1	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	115.640s	2432.374us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	243.690s	4782.185us	1	1	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	114.820s	2402.290us	1	1	100.00
		chip_sw_aes_smoketest	151.240s	3022.442us	1	1	100.00
		chip_sw_aon_timer_smoketest	215.470s	3649.122us	1	1	100.00
		chip_sw_clkmgr_smoketest	188.710s	2918.927us	1	1	100.00
		chip_sw_csrng_smoketest	112.230s	2268.722us	1	1	100.00
		chip_sw_entropy_src_smoketest	836.060s	6940.209us	1	1	100.00
		chip_sw_gpio_smoketest	148.580s	3122.242us	1	1	100.00
		chip_sw_hmac_smoketest	228.170s	3074.922us	1	1	100.00
		chip_sw_kmac_smoketest	180.210s	3527.555us	1	1	100.00
		chip_sw_otbn_smoketest	1279.700s	10467.215us	1	1	100.00
		chip_sw_pwrmgr_smoketest	331.660s	6715.814us	1	1	100.00
		chip_sw_pwrmgr_usbdev_smoketest	335.440s	6854.557us	1	1	100.00
		chip_sw_rv_plic_smoketest	139.270s	2962.000us	1	1	100.00
		chip_sw_rv_timer_smoketest	163.100s	2324.755us	1	1	100.00
		chip_sw_rstmgr_smoketest	124.770s	2361.759us	1	1	100.00
		chip_sw_sram_ctrl_smoketest	122.880s	2974.336us	1	1	100.00
		chip_sw_uart_smoketest	136.740s	2803.578us	1	1	100.00
V2	chip_sw_otp_smoketest	chip_sw_otp_ctrl_smoketest	132.030s	2316.391us	1	1	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	359.490s	5491.500us	1	1	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	7626.600s	62268.744us	1	1	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	2514.920s	14938.334us	1	1	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	127.250s	4839.294us	1	1	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	169.380s	3038.253us	0	1	0.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	159.180s	2865.460us	0	1	0.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	7279.810s	55334.495us	1	1	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	7336.390s	57022.609us	1	1	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	39.690s	2273.081us	0	1	0.00
V2	tl_d_illegal_access	chip_tl_errors	39.690s	2273.081us	0	1	0.00
V2	tl_d_outstanding_access	chip_csr_aliasing	5031.230s	40831.132us	1	1	100.00
		chip_same_csr_outstanding	2011.420s	28325.254us	1	1	100.00
		chip_csr_hw_reset	149.170s	5555.964us	1	1	100.00
		chip_csr_rw	324.090s	5680.326us	1	1	100.00
V2	tl_d_partial_access	chip_csr_aliasing	5031.230s	40831.132us	1	1	100.00
		chip_same_csr_outstanding	2011.420s	28325.254us	1	1	100.00
		chip_csr_hw_reset	149.170s	5555.964us	1	1	100.00
		chip_csr_rw	324.090s	5680.326us	1	1	100.00
V2	xbar_base_random_sequence	xbar_random	17.250s	259.438us	1	1	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	4.280s	43.314us	1	1	100.00
		xbar_smoke_large_delays	37.470s	5937.566us	1	1	100.00
		xbar_smoke_slow_rsp	47.840s	4922.730us	1	1	100.00
		xbar_random_zero_delays	31.030s	555.199us	1	1	100.00
		xbar_random_large_delays	224.610s	38999.951us	1	1	100.00
		xbar_random_slow_rsp	87.830s	10290.603us	1	1	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	18.120s	233.734us	1	1	100.00
		xbar_error_and_unmapped_addr	8.320s	271.815us	1	1	100.00
V2	xbar_error_cases	xbar_error_random	41.340s	1981.436us	1	1	100.00
		xbar_error_and_unmapped_addr	8.320s	271.815us	1	1	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	57.340s	2540.651us	1	1	100.00
		xbar_access_same_device_slow_rsp	355.980s	41283.613us	1	1	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	19.050s	427.579us	1	1	100.00
V2	xbar_stress_all	xbar_stress_all	20.420s	816.124us	1	1	100.00
		xbar_stress_all_with_error	28.010s	1217.068us	1	1	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	391.430s	4112.415us	1	1	100.00
		xbar_stress_all_with_reset_error	481.870s	19352.975us	1	1	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	2514.920s	14938.334us	1	1	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	2234.060s	32974.476us	1	1	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	2593.500s	15506.029us	1	1	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	2123.960s	12693.596us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	2757.810s	15797.131us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	2622.300s	15530.618us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	2588.600s	15088.188us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	2568.920s	18147.910us	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	22.670s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	22.830s	10.200us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	25.930s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	17.220s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	21.400s	10.160us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	26.940s	10.100us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	22.680s	10.340us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	20.520s	10.120us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	17.390s	10.320us	0	1	0.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	20.320s	10.100us	0	1	0.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	20.110s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	17.370s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	17.140s	10.180us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	16.990s	10.260us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	17.920s	10.100us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	24.360s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	17.350s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	18.040s	10.380us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	17.330s	10.120us	0	1	0.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	23.600s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	18.780s	10.140us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	17.840s	10.400us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	18.430s	10.300us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	16.380s	10.360us	0	1	0.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	19.970s	10.360us	0	1	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	1940.960s	11394.601us	1	1	100.00
		rom_e2e_asm_init_dev	2511.470s	16039.581us	1	1	100.00
		rom_e2e_asm_init_prod	2590.940s	15787.027us	1	1	100.00
		rom_e2e_asm_init_prod_end	2425.360s	15745.535us	1	1	100.00
		rom_e2e_asm_init_rma	2308.300s	15237.846us	1	1	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas	2387.720s	15564.953us	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_no_meas	2490.000s	15131.856us	1	1	100.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas	2369.900s	15449.492us	1	1	100.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	2533.620s	15971.535us	1	1	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3317.110s	34695.196us	0	1	0.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3317.110s	34695.196us	0	1	0.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	136.420s	3103.821us	1	1	100.00
		chip_sw_aes_enc_jitter_en	198.560s	2799.012us	1	1	100.00
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	135.940s	2658.789us	1	1	100.00
V2	chip_sw_aes_idle	chip_sw_aes_idle	144.240s	2816.798us	1	1	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	1616.890s	10944.203us	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	128.880s	2604.851us	0	1	0.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	291.560s	4855.151us	1	1	100.00
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	401.790s	4782.987us	1	1	100.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs_0	581.410s	5539.126us	1	1	100.00
		chip_plic_all_irqs_10	314.640s	3478.732us	1	1	100.00
		chip_plic_all_irqs_20	393.320s	4494.396us	1	1	100.00
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	185.610s	3398.772us	1	1	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	1079.760s	13467.180us	1	1	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	195.390s	3692.844us	1	1	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	117.420s	2493.271us	0	1	0.00
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	0.000s	0.000us	0	1	0.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	941.780s	6751.162us	1	1	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	991.650s	7938.459us	1	1	100.00
V2	chip_sw_alert_handler_ping_ok	chip_sw_alert_handler_ping_ok	793.600s	7806.705us	1	1	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	8824.080s	255708.929us	1	1	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	228.210s	3546.780us	1	1	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	331.660s	6715.814us	1	1	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	228.210s	3546.780us	1	1	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	431.600s	7696.865us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	431.600s	7696.865us	0	1	0.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	236.690s	7029.651us	1	1	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	257.330s	4904.807us	1	1	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	613.860s	5675.649us	1	1	100.00
		chip_sw_aes_idle	144.240s	2816.798us	1	1	100.00
		chip_sw_hmac_enc_idle	162.000s	2924.486us	1	1	100.00
		chip_sw_kmac_idle	143.390s	2449.634us	1	1	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	185.330s	4091.271us	1	1	100.00
		chip_sw_clkmgr_off_hmac_trans	242.750s	5207.571us	1	1	100.00
		chip_sw_clkmgr_off_kmac_trans	276.400s	4943.037us	1	1	100.00
		chip_sw_clkmgr_off_otbn_trans	176.360s	5206.287us	1	1	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	569.020s	8239.531us	1	1	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	349.540s	3700.075us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	343.170s	4741.332us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	376.920s	4373.483us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	348.320s	5146.150us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	397.950s	4693.901us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	346.680s	4133.100us	1	1	100.00
		chip_sw_ast_clk_outputs	536.330s	6960.285us	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	460.510s	9112.423us	1	1	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	376.920s	4373.483us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	348.320s	5146.150us	1	1	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	321.010s	4671.559us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	596.280s	5781.991us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3428.800s	19151.090us	1	1	100.00
		chip_sw_aes_enc_jitter_en	198.560s	2799.012us	1	1	100.00
		chip_sw_edn_entropy_reqs_jitter	779.340s	6640.829us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	134.660s	2512.085us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1191.760s	10344.138us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	206.340s	3200.939us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	361.410s	4225.301us	1	1	100.00
		chip_sw_clkmgr_jitter	144.710s	3369.148us	1	1	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	134.490s	2778.855us	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	362.260s	3950.814us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	647.880s	7061.597us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	3065.080s	24014.261us	1	1	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	114.230s	2963.782us	1	1	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	129.790s	2596.300us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	952.100s	10295.973us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	143.280s	3173.217us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	280.360s	4123.192us	1	1	100.00
		chip_sw_flash_init_reduced_freq	1118.010s	18487.621us	1	1	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	5322.850s	54749.426us	1	1	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	536.330s	6960.285us	1	1	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	361.860s	5059.545us	1	1	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	200.390s	3155.934us	1	1	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	401.790s	4782.987us	1	1	100.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	941.780s	6751.162us	1	1	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	684.730s	5654.358us	1	1	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	135.980s	2811.529us	0	1	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	426.780s	7135.835us	1	1	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	144.870s	3399.330us	1	1	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	3992.720s	24635.293us	1	1	100.00
		chip_sw_entropy_src_ast_rng_req	116.920s	2758.083us	1	1	100.00
		chip_sw_edn_entropy_reqs	711.190s	7205.328us	1	1	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	116.920s	2758.083us	1	1	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	684.730s	5654.358us	1	1	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	118.770s	2506.939us	1	1	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	1237.260s	23325.242us	1	1	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	578.980s	5582.941us	1	1	100.00
		chip_sw_flash_ctrl_access_jitter_en	596.280s	5781.991us	1	1	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	395.240s	4309.856us	1	1	100.00
		chip_sw_flash_ctrl_ops_jitter_en	321.010s	4671.559us	1	1	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	3779.640s	44076.377us	1	1	100.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	1237.260s	23325.242us	1	1	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	240.760s	3593.959us	1	1	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	719.510s	7420.743us	1	1	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	298.230s	4234.716us	1	1	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	3779.640s	44076.377us	1	1	100.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	298.230s	4234.716us	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	298.230s	4234.716us	1	1	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	298.230s	4234.716us	1	1	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	298.230s	4234.716us	1	1	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	401.790s	4782.987us	1	1	100.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	99.990s	5416.035us	1	1	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	501.920s	4911.594us	1	1	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	457.410s	4892.736us	1	1	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	457.410s	4892.736us	1	1	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	150.180s	3252.145us	1	1	100.00
		chip_sw_hmac_enc_jitter_en	134.660s	2512.085us	1	1	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	162.000s	2924.486us	1	1	100.00
V2	chip_sw_hmac_all_configurations	chip_sw_hmac_oneshot	792.140s	6498.715us	1	1	100.00
V2	chip_sw_hmac_multistream_mode	chip_sw_hmac_multistream	279.040s	4267.484us	1	1	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	333.630s	4767.852us	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx1	390.380s	4294.114us	1	1	100.00
		chip_sw_i2c_host_tx_rx_idx2	394.760s	5164.891us	1	1	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	286.840s	3903.149us	1	1	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	719.510s	7420.743us	1	1	100.00
		chip_sw_keymgr_key_derivation_jitter_en	1191.760s	10344.138us	1	1	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	1616.170s	12247.592us	1	1	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	1616.890s	10944.203us	1	1	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	2746.010s	15815.967us	1	1	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	187.910s	3110.419us	1	1	100.00
		chip_sw_kmac_mode_kmac	156.870s	2411.678us	1	1	100.00
		chip_sw_kmac_mode_kmac_jitter_en	206.340s	3200.939us	1	1	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	719.510s	7420.743us	1	1	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	214.090s	5019.588us	1	1	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	121.180s	2336.576us	1	1	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	534.530s	4987.703us	1	1	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	143.390s	2449.634us	1	1	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	291.560s	4855.151us	1	1	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	90.650s	3089.747us	1	1	100.00
		chip_tap_straps_rma	206.030s	4871.594us	1	1	100.00
		chip_tap_straps_prod	109.780s	3030.175us	1	1	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	132.850s	2760.915us	1	1	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	214.090s	5019.588us	1	1	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	214.090s	5019.588us	1	1	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	214.090s	5019.588us	1	1	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	1216.020s	9941.394us	1	1	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_prim_tl_access	99.990s	5416.035us	1	1	100.00
		chip_rv_dm_lc_disabled	83.240s	4460.631us	0	1	0.00
		chip_sw_flash_ctrl_lc_rw_en	298.230s	4234.716us	1	1	100.00
		chip_sw_flash_rma_unlocked	3779.640s	44076.377us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	184.470s	3130.401us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	452.540s	6261.931us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	478.360s	6871.490us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	499.440s	5429.157us	0	1	0.00
		chip_sw_lc_ctrl_transition	214.090s	5019.588us	1	1	100.00
		chip_sw_keymgr_key_derivation	719.510s	7420.743us	1	1	100.00
		chip_sw_rom_ctrl_integrity_check	323.990s	8110.373us	1	1	100.00
		chip_sw_sram_ctrl_execution_main	486.540s	8355.880us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	460.510s	9112.423us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	349.540s	3700.075us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	343.170s	4741.332us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	376.920s	4373.483us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	348.320s	5146.150us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	397.950s	4693.901us	1	1	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	346.680s	4133.100us	1	1	100.00
		chip_tap_straps_dev	90.650s	3089.747us	1	1	100.00
		chip_tap_straps_rma	206.030s	4871.594us	1	1	100.00
		chip_tap_straps_prod	109.780s	3030.175us	1	1	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	117.730s	3108.547us	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	98.770s	3186.941us	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	100.020s	3450.702us	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	163.410s	3847.860us	1	1	100.00
V2	chip_lc_test_locked	chip_rv_dm_lc_disabled	83.240s	4460.631us	0	1	0.00
		chip_sw_lc_walkthrough_testunlocks	1297.940s	25653.403us	1	1	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	3709.150s	50208.920us	1	1	100.00
		chip_sw_lc_walkthrough_prod	3742.940s	48171.180us	1	1	100.00
		chip_sw_lc_walkthrough_prodend	640.700s	9636.477us	1	1	100.00
		chip_sw_lc_walkthrough_rma	3543.540s	47329.706us	1	1	100.00
		chip_sw_lc_walkthrough_testunlocks	1297.940s	25653.403us	1	1	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	71.650s	2684.407us	1	1	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	63.050s	2773.133us	1	1	100.00
		rom_volatile_raw_unlock	61.740s	2484.552us	1	1	100.00
V2	chip_sw_otbn_op	chip_sw_otbn_ecdsa_op_irq	3333.330s	16424.654us	1	1	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	3428.800s	19151.090us	1	1	100.00
V2	chip_sw_otbn_rnd_entropy	chip_sw_otbn_randomness	613.860s	5675.649us	1	1	100.00
V2	chip_sw_otbn_urnd_entropy	chip_sw_otbn_randomness	613.860s	5675.649us	1	1	100.00
V2	chip_sw_otbn_idle	chip_sw_otbn_randomness	613.860s	5675.649us	1	1	100.00
V2	chip_sw_otbn_mem_scramble	chip_sw_otbn_mem_scramble	276.830s	3305.106us	1	1	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	214.090s	5019.588us	1	1	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	1237.260s	23325.242us	1	1	100.00
		chip_sw_otbn_mem_scramble	276.830s	3305.106us	1	1	100.00
		chip_sw_keymgr_key_derivation	719.510s	7420.743us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	398.170s	4951.031us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	160.520s	3169.588us	1	1	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	1237.260s	23325.242us	1	1	100.00
		chip_sw_otbn_mem_scramble	276.830s	3305.106us	1	1	100.00
		chip_sw_keymgr_key_derivation	719.510s	7420.743us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access	398.170s	4951.031us	1	1	100.00
		chip_sw_rv_core_ibex_icache_invalidate	160.520s	3169.588us	1	1	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	214.090s	5019.588us	1	1	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	279.340s	4893.816us	1	1	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	132.850s	2760.915us	1	1	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_prim_tl_access	99.990s	5416.035us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	184.470s	3130.401us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_dev	452.540s	6261.931us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_prod	478.360s	6871.490us	1	1	100.00
		chip_sw_otp_ctrl_lc_signals_rma	499.440s	5429.157us	0	1	0.00
		chip_sw_lc_ctrl_transition	214.090s	5019.588us	1	1	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	99.990s	5416.035us	1	1	100.00
V2	chip_sw_otp_ctrl_dai_lock	chip_sw_otp_ctrl_dai_lock	1179.490s	9847.788us	1	1	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	259.390s	7361.705us	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	1275.260s	27113.424us	1	1	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	247.350s	6664.797us	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	256.940s	7592.714us	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	300.140s	6179.603us	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	848.200s	20694.604us	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	987.600s	14235.293us	1	1	100.00
		chip_sw_aon_timer_wdog_bite_reset	431.600s	7696.865us	0	1	0.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	669.850s	10835.198us	0	1	0.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	365.960s	4141.483us	1	1	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	259.390s	7361.705us	1	1	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	183.190s	3878.616us	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	1555.900s	27733.944us	1	1	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	221.510s	5367.441us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	246.230s	6143.104us	1	1	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	207.280s	6040.214us	0	1	0.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	548.640s	7534.612us	1	1	100.00
		chip_sw_pwrmgr_all_reset_reqs	975.520s	10992.291us	1	1	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	1806.180s	30112.404us	1	1	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	174.490s	3279.139us	1	1	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	401.790s	4782.987us	1	1	100.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	323.990s	8110.373us	1	1	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	323.990s	8110.373us	1	1	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	975.520s	10992.291us	1	1	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	207.280s	6040.214us	0	1	0.00
		chip_sw_pwrmgr_wdog_reset	365.960s	4141.483us	1	1	100.00
		chip_sw_pwrmgr_smoketest	331.660s	6715.814us	1	1	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	202.940s	3758.485us	1	1	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	335.540s	4758.299us	0	1	0.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	172.450s	2924.959us	1	1	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	1079.760s	13467.180us	1	1	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	145.920s	2989.540us	1	1	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	401.790s	4782.987us	1	1	100.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	991.650s	7938.459us	1	1	100.00
V2	chip_sw_nmi_irq	chip_sw_rv_core_ibex_nmi_irq	464.070s	4258.300us	1	1	100.00
V2	chip_sw_rv_core_ibex_rnd	chip_sw_rv_core_ibex_rnd	489.520s	4822.396us	1	1	100.00
V2	chip_sw_rv_core_ibex_address_translation	chip_sw_rv_core_ibex_address_translation	147.330s	2875.966us	1	1	100.00
V2	chip_sw_rv_core_ibex_icache_scrambled_access	chip_sw_rv_core_ibex_icache_invalidate	160.520s	3169.588us	1	1	100.00
V2	chip_sw_rv_core_ibex_fault_dump	chip_sw_rstmgr_cpu_info	335.540s	4758.299us	0	1	0.00
V2	chip_sw_rv_core_ibex_double_fault	chip_sw_rstmgr_cpu_info	335.540s	4758.299us	0	1	0.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	701.190s	10462.739us	1	1	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	929.830s	12862.585us	1	1	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	202.940s	3758.485us	1	1	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	213.170s	4510.934us	1	1	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	278.050s	5933.604us	1	1	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	206.030s	4871.594us	1	1	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	83.240s	4460.631us	0	1	0.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	581.410s	5539.126us	1	1	100.00
		chip_plic_all_irqs_10	314.640s	3478.732us	1	1	100.00
		chip_plic_all_irqs_20	393.320s	4494.396us	1	1	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	144.370s	3464.884us	1	1	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	136.640s	3180.750us	1	1	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	2514.920s	14938.334us	1	1	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	340.880s	5214.418us	1	1	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	169.390s	3136.105us	0	1	0.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	230.890s	3193.546us	1	1	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	179.020s	3550.282us	1	1	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	398.170s	4951.031us	1	1	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	361.410s	4225.301us	1	1	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	358.130s	6354.024us	1	1	100.00
		chip_sw_sleep_sram_ret_contents_scramble	378.720s	8100.521us	1	1	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	486.540s	8355.880us	1	1	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	401.790s	4782.987us	1	1	100.00
		chip_sw_data_integrity_escalation	362.640s	4919.027us	1	1	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	548.640s	7534.612us	1	1	100.00
		chip_sw_sysrst_ctrl_reset	817.200s	21042.034us	1	1	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	143.490s	2907.631us	1	1	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	184.910s	3496.482us	1	1	100.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	368.490s	4471.812us	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	817.200s	21042.034us	1	1	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	817.200s	21042.034us	1	1	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	2512.200s	20055.904us	1	1	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	2512.200s	20055.904us	1	1	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	316.390s	5993.361us	1	1	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	3317.110s	34695.196us	0	1	0.00
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	157.880s	3031.513us	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	119.610s	2083.942us	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	282.020s	3575.689us	1	1	100.00
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	302.370s	3412.782us	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	1055.580s	8389.129us	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	5042.520s	32136.263us	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	1808.260s	12358.956us	1	1	100.00
V2	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore	165.900s	3448.178us	1	1	100.00
V2		TOTAL			233	275	84.73
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	139.220s	2384.434us	1	1	100.00
V2S	chip_sw_rv_core_ibex_lockstep_glitch	chip_sw_rv_core_ibex_lockstep_glitch	137.970s	2658.126us	1	1	100.00
V2S		TOTAL			2	2	100.00
V3	chip_sw_coremark	chip_sw_coremark	9261.290s	72260.874us	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	1052.320s	6526.263us	1	1	100.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	144.920s	3223.586us	0	1	0.00
		rom_e2e_jtag_debug_dev	1216.590s	11879.409us	1	1	100.00
		rom_e2e_jtag_debug_rma	1224.950s	12128.978us	1	1	100.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	248.670s	5510.730us	1	1	100.00
		rom_e2e_jtag_inject_dev	164.840s	4288.809us	1	1	100.00
		rom_e2e_jtag_inject_rma	180.010s	4396.521us	1	1	100.00
V3	rom_e2e_self_hash	rom_e2e_self_hash	9.586s	0.000us	0	1	0.00
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	514.310s	5179.131us	1	1	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	290.760s	2448.880us	1	1	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	1110.800s	7618.833us	1	1	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	1366.580s	10026.387us	1	1	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	224.900s	2650.515us	1	1	100.00
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	546.520s	4784.533us	1	1	100.00
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	150.620s	2801.773us	1	1	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	171.780s	3002.998us	0	1	0.00
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	196.390s	5635.372us	1	1	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	217.590s	4167.527us	1	1	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	975.520s	10992.291us	1	1	100.00
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	144.920s	3223.586us	0	1	0.00
		rom_e2e_jtag_debug_dev	1216.590s	11879.409us	1	1	100.00
		rom_e2e_jtag_debug_rma	1224.950s	12128.978us	1	1	100.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	313.650s	5497.296us	1	1	100.00
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	401.790s	4782.987us	1	1	100.00
V3	tick_configuration	chip_sw_rv_timer_systick_test	5698.550s	39019.941us	1	1	100.00
V3	counter_wrap	chip_sw_rv_timer_systick_test	5698.550s	39019.941us	1	1	100.00
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_pinmux_sleep_retention	116.120s	3355.433us	1	1	100.00
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	368.020s	4137.276us	1	1	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	3058.130s	18606.511us	1	1	100.00
V3		TOTAL			20	23	86.96
	Unmapped tests	chip_sival_flash_info_access	171.130s	2766.020us	1	1	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	419.000s	5725.151us	1	1	100.00
		chip_sw_otp_ctrl_rot_auth_config	1796.060s	22029.315us	0	1	0.00
		chip_sw_otp_ctrl_ecc_error_vendor_test	161.820s	2832.594us	1	1	100.00
		chip_sw_otp_ctrl_descrambling	192.800s	2948.124us	1	1	100.00
		chip_sw_pwrmgr_lowpower_cancel	197.780s	3777.749us	1	1	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.869s	0.000us	0	1	0.00
		chip_sw_flash_ctrl_write_clear	171.300s	2773.520us	1	1	100.00
		TOTAL			278	326	85.28

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
81.13	94.27	89.34	91.36	57.14	93.68	96.44	45.70

Failure Buckets

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 11 failures:
- Test rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.41536492661213217773743089825861002888743484797312586926314854947223718543983
    Line 483, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.25270130772987035390367738154202801106556816102695602118938837178111716667447
    Line 504, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.19040738664919044258031756854265159587729833106906559788029040854378676916093
    Line 505, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.40447845679440258367276120831305996489955844623211535284653318211112165252014
    Line 514, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end/latest/run.log
```
  UVM_FATAL @  10.320001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_bad_b_good_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.34557482914447730399424070431830509716847678543968880926714468169843070783992
    Line 500, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma/latest/run.log
```
  UVM_FATAL @  10.100001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- ... and 6 more tests.
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 5 failures:
- Test rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.12132367686315482606382745795563456370455600280848024049952676450607191487279
    Line 473, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_dev has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.26572102646497356422437282938259263205938786369779867421509146776400171592775
    Line 475, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.200001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.91701514838880994475587602052679221527401172594828503350376019243707260379094
    Line 499, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.120001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.120001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.69869003606836094062612260108645999854791121351706112367840363104010505724861
    Line 501, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.340001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_boot_policy_valid_a_good_b_bad_rma has 1 failures.
  - 0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.79634717925580411448814322183295189925286603595153666033777688185800252873142
    Line 489, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.160001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank1Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.160001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(rstreqs[*] && (reset_cause == HwReq))' has 3 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.101467264039676326849246404880459816287017878945274957232641827246265966084055
    Line 398, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 6040.214000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 6040.214000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_deep_sleep_por_reset.92647475263476902069051784722698753664973997939932995018541428539522461195049
    Line 407, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
      Offending '(rstreqs[0] && (reset_cause == HwReq))'
  UVM_ERROR @ 7592.714000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7592.714000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_aon_timer_wdog_bite_reset has 1 failures.
  - 0.chip_sw_aon_timer_wdog_bite_reset.104437353415405983361056008470223834348592969205545382594819962947681548744725
    Line 404, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_aon_timer_wdog_bite_reset/latest/run.log
```
      Offending '(rstreqs[1] && (reset_cause == HwReq))'
  UVM_ERROR @ 7696.865000 us: (pwrmgr_rstreqs_sva_if.sv:49) [ASSERT FAILED] HwResetOn_A
  UVM_INFO @ 7696.865000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_*.signed.*.scr.vmem could not be opened for r mode has 3 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.109636233526144043233268003036636078974572462285002513990046135991344551052276
    Line 442, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_prod_end has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.38443340772488734421961949015441776675643039079335056488528034008170713153830
    Line 460, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_nothing_b_bad_rma has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.38495152849455255659717629834378686010976297670222634371807713454635799737584
    Line 528, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_prod_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))' has 2 failures:
- Test chip_sw_otp_ctrl_escalation has 1 failures.
  - 0.chip_sw_otp_ctrl_escalation.84598799606256901966161265251233854817029241721457714982294637864266672019598
    Line 397, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_escalation/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 3002.997544 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 3002.997544 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 1 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.72913644094806393821763415280457300677835174129995135308980141639356327935696
    Line 396, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
      Offending '(!$fell(lc_ctrl_pkg::lc_tx_test_true_strict(lc_init_done_o)))'
  UVM_ERROR @ 2811.528892 us: (lc_ctrl.sv:878) [ASSERT FAILED] LcInitDoneSticky_A
  UVM_INFO @ 2811.528892 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

Job returned non-zero exit code has 2 failures:

Test chip_sw_pwrmgr_sleep_wake_5_bug has 1 failures.

0.chip_sw_pwrmgr_sleep_wake_5_bug.67951881328055156304394346772549781179337544685398560702933690650444500334911
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_sleep_wake_5_bug/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  ERROR: no such target '//sw/device/tests:pwrmgr_sleep_wake_5_bug_test_sim_dv': target 'pwrmgr_sleep_wake_5_bug_test_sim_dv' not declared in package 'sw/device/tests' defined by /nightly/current_run/opentitan/sw/device/tests/BUILD
  INFO: Elapsed time: 0.154s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

Test rom_e2e_self_hash has 1 failures.

0.rom_e2e_self_hash.101095615012486917129809979360348781292276203451950238362010786667746367059958
Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  Computing main repo mapping:
  Loading:
  Loading: 0 packages loaded
  WARNING: Target pattern parsing failed.
  ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  ERROR: no such target '//sw/device/silicon_creator/rom/e2e/release:rom_e2e_self_hash_test_sim_dv': target 'rom_e2e_self_hash_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/release' defined by /nightly/current_run/opentitan/sw/device/silicon_creator/rom/e2e/release/BUILD
  INFO: Elapsed time: 0.176s
  INFO: 0 processes.
  ERROR: Build did NOT complete successfully
  make: *** [/nightly/current_run/opentitan/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.53626632226689985381487244030233405611155392390072745779953637826554355029819
    Line 506, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.380001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.57516235678468633514812262907991091228085352141458683485869014042774342722926
    Line 496, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 2 failures:
- Test rom_e2e_sigverify_always_a_bad_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_bad_dev.101887237000849498410070231877050217141425387288908195559853215608165740154501
    Line 523, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.300001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_sigverify_always_a_bad_b_nothing_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.19152385423897625372535294543147606373364277231025245137957269759108262553524
    Line 516, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev/latest/run.log
```
  UVM_FATAL @  10.360001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_a_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.360001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32237) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_tl_errors has 1 failures.

0.chip_tl_errors.57809530305597709888293212822785838321318960633896099729551343088682457775322
Line 214, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_tl_errors/latest/run.log

  UVM_ERROR @ 2273.081032 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32237) { a_addr: 'h105f4  a_data: 'h1c9b2e5b  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h36  a_opcode: 'h4  a_user: 'h1ba60  d_param: 'h0  d_source: 'h36  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 2273.081032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (cip_base_vseq.sv:642) [chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (* [*] vs * [*]) addr * read out mismatch has 1 failures:
- Test chip_rv_dm_lc_disabled has 1 failures.
  - 0.chip_rv_dm_lc_disabled.83063220644741983270800117919669530169536059123528953659878227453068247254473
    Line 208, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_rv_dm_lc_disabled/latest/run.log
```
  UVM_ERROR @ 4460.630922 us: (cip_base_vseq.sv:642) [uvm_test_top.env.virtual_sequencer.chip_rv_dm_lc_disabled_vseq] Check failed masked_data == exp_data (0 [0x0] vs 4294967295 [0xffffffff]) addr 0x10594 read out mismatch
  UVM_INFO @ 4460.630922 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32245) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_csr_mem_rw_with_rand_reset has 1 failures.

0.chip_csr_mem_rw_with_rand_reset.111022888086265790983515690663309588026180603180072893946097796054034795691185
Line 221, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

  UVM_ERROR @ 1981.577260 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (0 [0x0] vs 1 [0x1]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@32245) { a_addr: 'h107dc  a_data: 'h57c6979  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1f  a_opcode: 'h4  a_user: 'h1bd07  d_param: 'h0  d_source: 'h1f  d_data: 'h0  d_size: 'h2  d_opcode: 'h1  d_error: 'h0  d_sink: 'h0  d_user: 'hd2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 1981.577260 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR @ * us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty has 1 failures:
- Test chip_sw_spi_device_pass_through_collision has 1 failures.
  - 0.chip_sw_spi_device_pass_through_collision.66510746097424452577436870137745028551886078641654702375964860404181144620020
    Line 408, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_spi_device_pass_through_collision/latest/run.log
```
  UVM_ERROR @ 3136.104820 us: (sw_logger_if.sv:526) [spi_passthrough_test_sim_dv(sw/device/tests/sim_dv/spi_passthrough_test.c:382)] CHECK-fail: irq == kDtSpiDeviceIrqUploadCmdfifoNotEmpty
  UVM_INFO @ 3136.104820 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to * has 1 failures:
- Test chip_sw_otp_ctrl_lc_signals_rma has 1 failures.
  - 0.chip_sw_otp_ctrl_lc_signals_rma.76012089068094693131002370445911598410190768770321072908645972786373517558583
    Line 421, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_lc_signals_rma/latest/run.log
```
  UVM_ERROR @ 5429.157374 us: (sw_logger_if.sv:526) [otp_ctrl_lc_signals_test_sim_dv(sw/device/lib/testing/otp_ctrl_testutils.c:39)] Expected a DAI error for access to 0x0
  UVM_INFO @ 5429.157374 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:* = ErrorError has 1 failures:
- Test chip_sw_otp_ctrl_rot_auth_config has 1 failures.
  - 0.chip_sw_otp_ctrl_rot_auth_config.57807293120336634307299811952466572456118380801741210490547836010559410644770
    Line 439, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_otp_ctrl_rot_auth_config/latest/run.log
```
  UVM_ERROR @ 22029.314947 us: (sw_logger_if.sv:526) [otp_ctrl_rot_auth_config_test_sim_dv(sw/device/tests/otp_ctrl_rot_auth_config_test.c:22)] CHECK-STATUS-fail: @@@:0 = ErrorError
  UVM_INFO @ 22029.314947 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (cip_base_scoreboard.sv:549) [scoreboard] Check failed item.d_error == exp_d_error (* [*] vs * [*]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@117933) { a_addr: * a_data: * a_mask: * a_size: * a_param: * a_source: * a_opcode: * a_user: * d_param: * d_source: * d_data: * d_size: * d_opcode: * d_error: * d_sink: * d_user: * a_valid_delay: * d_valid_delay: * a_valid_len: * d_valid_len: * req_abort_after_a_valid_len: * rsp_abort_after_d_valid_len: * req_completed: * rsp_completed: * tl_intg_err_type: TlIntgErrNone max_ecc_errors: * } has 1 failures:

Test chip_sw_rstmgr_cpu_info has 1 failures.

0.chip_sw_rstmgr_cpu_info.79551689187763428403998429486352493534887067533379762904816996012947826420414
Line 419, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_rstmgr_cpu_info/latest/run.log

  UVM_ERROR @ 4758.299136 us: (cip_base_scoreboard.sv:549) [uvm_test_top.env.scoreboard] Check failed item.d_error == exp_d_error (1 [0x1] vs 0 [0x0]) On interface chip_reg_block, TL item: req: (cip_tl_seq_item@117933) { a_addr: 'h8  a_data: 'h0  a_mask: 'hf  a_size: 'h2  a_param: 'h0  a_source: 'h1  a_opcode: 'h0  a_user: 'h259aa  d_param: 'h0  d_source: 'h1  d_data: 'h0  d_size: 'h2  d_opcode: 'h0  d_error: 'h1  d_sink: 'h0  d_user: 'h1f2a  a_valid_delay: 'h0  d_valid_delay: 'h0  a_valid_len: 'h0  d_valid_len: 'h0  req_abort_after_a_valid_len: 'h0  rsp_abort_after_d_valid_len: 'h0  req_completed: 'h0  rsp_completed: 'h0  tl_intg_err_type: TlIntgErrNone  max_ecc_errors: 'h3  }
  , unmapped_err: 0, mem_access_err: 0, bus_intg_err: 0, byte_wr_err: 0, csr_size_err: 0, tl_item_err: 0, write_w_instr_type_err: 0, cfg.tl_mem_access_gated: 0 ecc_err: 0
  UVM_INFO @ 4758.299136 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:

Test chip_sw_pwrmgr_normal_sleep_all_reset_reqs has 1 failures.

0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.53160724472880189563950657242158797103747363749645839331485939873934507876262
Line 429, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs/latest/run.log

      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 7166872152ps failed at 7166872152ps
      Offending '(pend_req[h2d.a_source].pend == 0)'
  "src/lowrisc_tlul_common_0.1/rtl/tlul_assert.sv", 284: tb.dut.top_earlgrey.u_pwrmgr_aon.tlul_assert_device.gen_device.gen_h2d.pendingReqPerSrc_M: started at 7166955480ps failed at 7166955480ps
      Offending '(pend_req[h2d.a_source].pend == 0)'

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:317) virtual_sequencer [chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_adc_ctrl_sleep_debug_cable_wakeup has 1 failures.
  - 0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.54176966553547121169558920719077188303962932010541312059329141258484869645386
    Line 430, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup/latest/run.log
```
  UVM_ERROR @ 34695.195916 us: (chip_sw_base_vseq.sv:317) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_adc_ctrl_sleep_debug_cable_wakeup_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 18000000 ns

  UVM_INFO @ 34695.195916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert *! has 1 failures:
- Test chip_sw_alert_test has 1 failures.
  - 0.chip_sw_alert_test.90681771137642053233855017129525441982231899764633533020813954654207238291349
    Line 385, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_test/latest/run.log
```
  UVM_ERROR @ 2604.851432 us: (sw_logger_if.sv:526) [alert_test_sim_dv(hw/top_earlgrey/sw/autogen/tests/alert_test.c:307)] CHECK-fail: Expect alert 42!
  UVM_INFO @ 2604.851432 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0) has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_alerts.8048650801974351797015473597987659041291790593966470095748204445902664833183
    Line 390, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 2493.271258 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/ret_sram_testutils.c:67)] CHECK-fail: testing_utilities != ((void*)0)
  UVM_INFO @ 2493.271258 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job timed out after * minutes has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_pings has 1 failures.
  - 0.chip_sw_alert_handler_lpg_sleep_mode_pings.30195027782428686678935510415647586952213308818841720078138103491800752039128
    Log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_lpg_sleep_mode_pings/latest/run.log
```
  Job timed out after 240 minutes
```
UVM_ERROR @ * us: (chip_sw_power_idle_load_vseq.sv:91) virtual_sequencer [chip_sw_power_idle_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_idle_load has 1 failures.
  - 0.chip_sw_power_idle_load.62306904093636746996122677282797460753670426173868730908679881795187526638599
    Line 400, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_idle_load/latest/run.log
```
  UVM_ERROR @ 3038.253000 us: (chip_sw_power_idle_load_vseq.sv:91) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_idle_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 3038.253000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_sleep_load_vseq.sv:114) virtual_sequencer [chip_sw_power_sleep_load_vseq] PWMCH* : pkt* Clock period is wrong. rcv : * exp : * has 1 failures:
- Test chip_sw_power_sleep_load has 1 failures.
  - 0.chip_sw_power_sleep_load.1977330703837652908131920946368388656403745463778440101569893936197501144528
    Line 408, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_sleep_load/latest/run.log
```
  UVM_ERROR @ 2865.460000 us: (chip_sw_power_sleep_load_vseq.sv:114) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_power_sleep_load_vseq] PWMCH5 : pkt3 Clock period is wrong.  rcv : 2  exp : 32
  UVM_INFO @ 2865.460000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler has 1 failures:
- Test chip_sw_ast_clk_rst_inputs has 1 failures.
  - 0.chip_sw_ast_clk_rst_inputs.113176194959880038431663071593998564398567369332164545021463225581920043719452
    Line 414, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  UVM_ERROR @ 23519.953731 us: (sw_logger_if.sv:526) [ast_clk_rst_inputs_sim_dv(sw/device/tests/sim_dv/ast_clk_rst_inputs.c:147)] CHECK-fail: Recov alert not correctly observed in alert handler
  UVM_INFO @ 23519.953731 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0 has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.40533185030281631697009339460860412661060179868253781997684101616796446401675
    Line 497, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0/latest/run.log
```
  UVM_FATAL @  10.140001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_test_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_*.signed.*.scr.vmem could not be opened for r mode has 1 failures:
- Test rom_e2e_sigverify_always_a_nothing_b_bad_dev has 1 failures.
  - 0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.88395134833140023469765250886215942766103202430478510973089860657242514411862
    Line 472, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev/latest/run.log
```
  UVM_FATAL @  10.400001 us: (mem_bkdr_util.sv:597) [mem_bkdr_util[FlashBank0Data]] file empty_test_slot_b_corrupted_sim_dv.fake_ecdsa_dev_key_0.signed.64.scr.vmem could not be opened for r mode
  UVM_INFO @  10.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (jtag_rv_debugger.sv:784) [debugger] Index * appears to be out of bounds has 1 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.105726350296001071179894051451948189936662733513637682975152944837175054476147
    Line 439, in log /nightly/current_run/scratch/master/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 3223.585517 us: (jtag_rv_debugger.sv:784) [debugger] Index 3 appears to be out of bounds
  UVM_INFO @ 3223.585517 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```