Simulation Results: adc_ctrl

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.52
  • line
  • 99.05
  • cond
  • 95.45
  • toggle
  • 100.0
  • fsm
  • 91.89
  • branch
  • 98.58
  • assert
  • 95.79
  • group
  • 45.89
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 13.540s 5648.018us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.740s 604.307us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.680s 398.278us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 43.590s 26374.926us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 2.560s 855.116us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 2.150s 500.150us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.680s 398.278us 1 1 100.00
adc_ctrl_csr_aliasing 2.560s 855.116us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 284.230s 318324.877us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 488.810s 323743.819us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 501.510s 324787.196us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 796.600s 496621.584us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 311.650s 185102.196us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 87.490s 199180.315us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 143.520s 364176.896us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 270.270s 2000000.000us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 6.190s 4369.375us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 15.080s 31555.830us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 55.280s 120517.739us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 328.280s 683851.025us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 2.080s 471.894us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 0.940s 343.076us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.910s 800.021us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.910s 800.021us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.740s 604.307us 1 1 100.00
adc_ctrl_csr_rw 1.680s 398.278us 1 1 100.00
adc_ctrl_csr_aliasing 2.560s 855.116us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.350s 2400.219us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.740s 604.307us 1 1 100.00
adc_ctrl_csr_rw 1.680s 398.278us 1 1 100.00
adc_ctrl_csr_aliasing 2.560s 855.116us 1 1 100.00
adc_ctrl_same_csr_outstanding 2.350s 2400.219us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 4.400s 9612.926us 1 1 100.00
adc_ctrl_sec_cm 9.410s 3962.554us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 4.400s 9612.926us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 11.860s 19422.023us 1 1 100.00