| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| V3 |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 0.830s | 38.787us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.890s | 19.940us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.940s | 20.445us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| clkmgr_csr_bit_bash | 5.820s | 526.246us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| clkmgr_csr_aliasing | 1.230s | 52.124us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| clkmgr_csr_mem_rw_with_rand_reset | 0.970s | 57.501us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| clkmgr_csr_rw | 0.940s | 20.445us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 1.230s | 52.124us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| peri_enables | 1 | 1 | 100.00 | |||
| clkmgr_peri | 0.750s | 18.290us | 1 | 1 | 100.00 | |
| trans_enables | 1 | 1 | 100.00 | |||
| clkmgr_trans | 0.920s | 97.546us | 1 | 1 | 100.00 | |
| extclk | 1 | 1 | 100.00 | |||
| clkmgr_extclk | 0.780s | 14.353us | 1 | 1 | 100.00 | |
| clk_status | 1 | 1 | 100.00 | |||
| clkmgr_clk_status | 0.710s | 53.752us | 1 | 1 | 100.00 | |
| jitter | 1 | 1 | 100.00 | |||
| clkmgr_smoke | 0.830s | 38.787us | 1 | 1 | 100.00 | |
| frequency | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 2.450s | 709.553us | 1 | 1 | 100.00 | |
| frequency_timeout | 1 | 1 | 100.00 | |||
| clkmgr_frequency_timeout | 1.890s | 522.080us | 1 | 1 | 100.00 | |
| frequency_overflow | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 2.450s | 709.553us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| clkmgr_stress_all | 15.180s | 4377.128us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| clkmgr_alert_test | 0.770s | 21.625us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| clkmgr_tl_errors | 1.450s | 59.115us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| clkmgr_tl_errors | 1.450s | 59.115us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.890s | 19.940us | 1 | 1 | 100.00 | |
| clkmgr_csr_rw | 0.940s | 20.445us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 1.230s | 52.124us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 1.000s | 34.685us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| clkmgr_csr_hw_reset | 0.890s | 19.940us | 1 | 1 | 100.00 | |
| clkmgr_csr_rw | 0.940s | 20.445us | 1 | 1 | 100.00 | |
| clkmgr_csr_aliasing | 1.230s | 52.124us | 1 | 1 | 100.00 | |
| clkmgr_same_csr_outstanding | 1.000s | 34.685us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| clkmgr_sec_cm | 1.970s | 313.884us | 1 | 1 | 100.00 | |
| clkmgr_tl_intg_err | 2.490s | 631.734us | 1 | 1 | 100.00 | |
| shadow_reg_update_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.560s | 215.457us | 1 | 1 | 100.00 | |
| shadow_reg_read_clear_staged_value | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.560s | 215.457us | 1 | 1 | 100.00 | |
| shadow_reg_storage_error | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.560s | 215.457us | 1 | 1 | 100.00 | |
| shadowed_reset_glitch | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.560s | 215.457us | 1 | 1 | 100.00 | |
| shadow_reg_update_error_with_csr_rw | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors_with_csr_rw | 2.350s | 277.827us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| clkmgr_tl_intg_err | 2.490s | 631.734us | 1 | 1 | 100.00 | |
| sec_cm_meas_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| clkmgr_frequency | 2.450s | 709.553us | 1 | 1 | 100.00 | |
| sec_cm_timeout_clk_bkgn_chk | 1 | 1 | 100.00 | |||
| clkmgr_frequency_timeout | 1.890s | 522.080us | 1 | 1 | 100.00 | |
| sec_cm_meas_config_shadow | 1 | 1 | 100.00 | |||
| clkmgr_shadow_reg_errors | 1.560s | 215.457us | 1 | 1 | 100.00 | |
| sec_cm_idle_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_idle_intersig_mubi | 1.450s | 329.604us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_lc_ctrl_intersig_mubi | 0.960s | 28.595us | 1 | 1 | 100.00 | |
| sec_cm_lc_ctrl_clk_handshake_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_lc_clk_byp_req_intersig_mubi | 0.840s | 25.330us | 1 | 1 | 100.00 | |
| sec_cm_clk_handshake_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_clk_handshake_intersig_mubi | 0.790s | 27.203us | 1 | 1 | 100.00 | |
| sec_cm_div_intersig_mubi | 1 | 1 | 100.00 | |||
| clkmgr_div_intersig_mubi | 0.880s | 20.462us | 1 | 1 | 100.00 | |
| sec_cm_jitter_config_mubi | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.940s | 20.445us | 1 | 1 | 100.00 | |
| sec_cm_idle_ctr_redun | 1 | 1 | 100.00 | |||
| clkmgr_sec_cm | 1.970s | 313.884us | 1 | 1 | 100.00 | |
| sec_cm_meas_config_regwen | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.940s | 20.445us | 1 | 1 | 100.00 | |
| sec_cm_clk_ctrl_config_regwen | 1 | 1 | 100.00 | |||
| clkmgr_csr_rw | 0.940s | 20.445us | 1 | 1 | 100.00 | |
| prim_count_check | 1 | 1 | 100.00 | |||
| clkmgr_sec_cm | 1.970s | 313.884us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| regwen | 1 | 1 | 100.00 | |||
| clkmgr_regwen | 5.790s | 1458.135us | 1 | 1 | 100.00 | |
| stress_all_with_rand_reset | 1 | 1 | 100.00 | |||
| clkmgr_stress_all_with_rand_reset | 38.010s | 7123.823us | 1 | 1 | 100.00 | |