Simulation Results: csrng

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 94.74
  • block
  • 96.79
  • branch
  • 92.12
  • statement
  • 97.77
  • expression
  • 94.98
  • toggle
  • 91.65
  • fsm
  • 84.85
  • assertion
  • 92.74
  • covergroup
  • 76.11
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
csrng_smoke 3.000s 97.633us 1 1 100.00
csr_hw_reset 1 1 100.00
csrng_csr_hw_reset 3.000s 59.055us 1 1 100.00
csr_rw 1 1 100.00
csrng_csr_rw 2.000s 46.667us 1 1 100.00
csr_bit_bash 1 1 100.00
csrng_csr_bit_bash 19.000s 523.023us 1 1 100.00
csr_aliasing 1 1 100.00
csrng_csr_aliasing 4.000s 134.622us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
csrng_csr_mem_rw_with_rand_reset 3.000s 121.890us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
csrng_csr_rw 2.000s 46.667us 1 1 100.00
csrng_csr_aliasing 4.000s 134.622us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
interrupts 1 1 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
alerts 1 1 100.00
csrng_alert 7.000s 113.177us 1 1 100.00
err 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
cmds 1 1 100.00
csrng_cmds 148.000s 6429.246us 1 1 100.00
life cycle 1 1 100.00
csrng_cmds 148.000s 6429.246us 1 1 100.00
stress_all 1 1 100.00
csrng_stress_all 54.000s 2430.524us 1 1 100.00
intr_test 1 1 100.00
csrng_intr_test 2.000s 40.679us 1 1 100.00
alert_test 1 1 100.00
csrng_alert_test 3.000s 117.881us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
csrng_tl_errors 3.000s 52.225us 1 1 100.00
tl_d_illegal_access 1 1 100.00
csrng_tl_errors 3.000s 52.225us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
csrng_csr_hw_reset 3.000s 59.055us 1 1 100.00
csrng_csr_rw 2.000s 46.667us 1 1 100.00
csrng_csr_aliasing 4.000s 134.622us 1 1 100.00
csrng_same_csr_outstanding 5.000s 226.364us 1 1 100.00
tl_d_partial_access 4 4 100.00
csrng_csr_hw_reset 3.000s 59.055us 1 1 100.00
csrng_csr_rw 2.000s 46.667us 1 1 100.00
csrng_csr_aliasing 4.000s 134.622us 1 1 100.00
csrng_same_csr_outstanding 5.000s 226.364us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
csrng_tl_intg_err 5.000s 128.503us 1 1 100.00
csrng_sec_cm 4.000s 151.199us 1 1 100.00
sec_cm_config_regwen 2 2 100.00
csrng_csr_rw 2.000s 46.667us 1 1 100.00
csrng_regwen 2.000s 55.527us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
csrng_alert 7.000s 113.177us 1 1 100.00
sec_cm_intersig_mubi 1 1 100.00
csrng_stress_all 54.000s 2430.524us 1 1 100.00
sec_cm_main_sm_fsm_sparse 3 3 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
csrng_sec_cm 4.000s 151.199us 1 1 100.00
sec_cm_updrsp_fsm_sparse 3 3 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
csrng_sec_cm 4.000s 151.199us 1 1 100.00
sec_cm_update_fsm_sparse 3 3 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
csrng_sec_cm 4.000s 151.199us 1 1 100.00
sec_cm_blk_enc_fsm_sparse 3 3 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
csrng_sec_cm 4.000s 151.199us 1 1 100.00
sec_cm_outblk_fsm_sparse 3 3 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
csrng_sec_cm 4.000s 151.199us 1 1 100.00
sec_cm_gen_cmd_ctr_redun 3 3 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
csrng_sec_cm 4.000s 151.199us 1 1 100.00
sec_cm_drbg_upd_ctr_redun 3 3 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
csrng_sec_cm 4.000s 151.199us 1 1 100.00
sec_cm_drbg_gen_ctr_redun 3 3 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
csrng_sec_cm 4.000s 151.199us 1 1 100.00
sec_cm_ctrl_mubi 1 1 100.00
csrng_alert 7.000s 113.177us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
sec_cm_constants_lc_gated 1 1 100.00
csrng_stress_all 54.000s 2430.524us 1 1 100.00
sec_cm_sw_genbits_bus_consistency 1 1 100.00
csrng_alert 7.000s 113.177us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
csrng_tl_intg_err 5.000s 128.503us 1 1 100.00
sec_cm_aes_cipher_fsm_sparse 3 3 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
csrng_sec_cm 4.000s 151.199us 1 1 100.00
sec_cm_aes_cipher_fsm_redun 2 2 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
sec_cm_aes_cipher_ctrl_sparse 2 2 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
sec_cm_aes_cipher_fsm_local_esc 2 2 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
sec_cm_aes_cipher_ctr_redun 3 3 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
csrng_sec_cm 4.000s 151.199us 1 1 100.00
sec_cm_aes_cipher_data_reg_local_esc 2 2 100.00
csrng_intr 5.000s 142.228us 1 1 100.00
csrng_err 2.000s 19.965us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
csrng_stress_all_with_rand_reset 244.000s 16686.453us 1 1 100.00