Simulation Results: edn

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 83.68
  • line
  • 97.68
  • cond
  • 88.16
  • toggle
  • 83.67
  • fsm
  • 50.0
  • branch
  • 92.38
  • assert
  • 96.22
  • group
  • 77.67
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.970s 41.439us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.890s 64.659us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 40.755us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 2.090s 726.159us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.030s 95.195us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.070s 34.555us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 40.755us 1 1 100.00
edn_csr_aliasing 1.030s 95.195us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.380s 53.822us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.380s 53.822us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.380s 53.822us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.990s 37.186us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.080s 38.448us 1 1 100.00
errs 1 1 100.00
edn_err 1.060s 28.658us 1 1 100.00
disable 2 2 100.00
edn_disable 1.130s 12.737us 1 1 100.00
edn_disable_auto_req_mode 1.050s 56.457us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 1.920s 300.584us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.740s 30.985us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.850s 29.565us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.990s 88.920us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.990s 88.920us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.890s 64.659us 1 1 100.00
edn_csr_rw 0.790s 40.755us 1 1 100.00
edn_csr_aliasing 1.030s 95.195us 1 1 100.00
edn_same_csr_outstanding 1.180s 29.217us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.890s 64.659us 1 1 100.00
edn_csr_rw 0.790s 40.755us 1 1 100.00
edn_csr_aliasing 1.030s 95.195us 1 1 100.00
edn_same_csr_outstanding 1.180s 29.217us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 5.350s 913.077us 1 1 100.00
edn_tl_intg_err 1.750s 279.068us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.920s 49.296us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.080s 38.448us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.350s 913.077us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 5.350s 913.077us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 5.350s 913.077us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 5.350s 913.077us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.080s 38.448us 1 1 100.00
edn_sec_cm 5.350s 913.077us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.080s 38.448us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.750s 279.068us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 77.690s 45251.500us 1 1 100.00