Simulation Results: hmac

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.63
  • line
  • 99.74
  • cond
  • 95.9
  • toggle
  • 100.0
  • fsm
  • 94.12
  • branch
  • 99.01
  • assert
  • 96.42
  • group
  • 42.24
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 2.630s 69.004us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 1.020s 64.938us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.780s 50.877us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.060s 224.346us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 4.590s 5203.082us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 133.510s 21058.936us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.780s 50.877us 1 1 100.00
hmac_csr_aliasing 4.590s 5203.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 45.600s 7210.385us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 44.710s 1126.971us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 7.620s 684.326us 1 1 100.00
hmac_test_sha384_vectors 307.390s 69965.042us 1 1 100.00
hmac_test_sha512_vectors 360.770s 45519.134us 1 1 100.00
hmac_test_hmac256_vectors 9.750s 346.863us 1 1 100.00
hmac_test_hmac384_vectors 9.930s 282.006us 1 1 100.00
hmac_test_hmac512_vectors 8.340s 466.916us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 17.170s 4034.434us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 54.330s 5117.790us 1 1 100.00
error 1 1 100.00
hmac_error 23.810s 3412.518us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 101.050s 41151.633us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 2.630s 69.004us 1 1 100.00
hmac_long_msg 45.600s 7210.385us 1 1 100.00
hmac_back_pressure 44.710s 1126.971us 1 1 100.00
hmac_datapath_stress 54.330s 5117.790us 1 1 100.00
hmac_burst_wr 17.170s 4034.434us 1 1 100.00
hmac_stress_all 70.120s 7174.223us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 2.630s 69.004us 1 1 100.00
hmac_long_msg 45.600s 7210.385us 1 1 100.00
hmac_back_pressure 44.710s 1126.971us 1 1 100.00
hmac_datapath_stress 54.330s 5117.790us 1 1 100.00
hmac_wipe_secret 101.050s 41151.633us 1 1 100.00
hmac_test_sha256_vectors 7.620s 684.326us 1 1 100.00
hmac_test_sha384_vectors 307.390s 69965.042us 1 1 100.00
hmac_test_sha512_vectors 360.770s 45519.134us 1 1 100.00
hmac_test_hmac256_vectors 9.750s 346.863us 1 1 100.00
hmac_test_hmac384_vectors 9.930s 282.006us 1 1 100.00
hmac_test_hmac512_vectors 8.340s 466.916us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 2.630s 69.004us 1 1 100.00
hmac_long_msg 45.600s 7210.385us 1 1 100.00
hmac_back_pressure 44.710s 1126.971us 1 1 100.00
hmac_datapath_stress 54.330s 5117.790us 1 1 100.00
hmac_burst_wr 17.170s 4034.434us 1 1 100.00
hmac_error 23.810s 3412.518us 1 1 100.00
hmac_wipe_secret 101.050s 41151.633us 1 1 100.00
hmac_test_sha256_vectors 7.620s 684.326us 1 1 100.00
hmac_test_sha384_vectors 307.390s 69965.042us 1 1 100.00
hmac_test_sha512_vectors 360.770s 45519.134us 1 1 100.00
hmac_test_hmac256_vectors 9.750s 346.863us 1 1 100.00
hmac_test_hmac384_vectors 9.930s 282.006us 1 1 100.00
hmac_test_hmac512_vectors 8.340s 466.916us 1 1 100.00
hmac_stress_all 70.120s 7174.223us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 70.120s 7174.223us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.870s 13.235us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.690s 49.646us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 1.690s 288.494us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 1.690s 288.494us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 1.020s 64.938us 1 1 100.00
hmac_csr_rw 0.780s 50.877us 1 1 100.00
hmac_csr_aliasing 4.590s 5203.082us 1 1 100.00
hmac_same_csr_outstanding 1.470s 65.430us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 1.020s 64.938us 1 1 100.00
hmac_csr_rw 0.780s 50.877us 1 1 100.00
hmac_csr_aliasing 4.590s 5203.082us 1 1 100.00
hmac_same_csr_outstanding 1.470s 65.430us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_sec_cm 1.320s 168.597us 1 1 100.00
hmac_tl_intg_err 3.030s 1227.082us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 3.030s 1227.082us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 2.630s 69.004us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.640s 84.863us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 10.880s 4150.175us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 1.120s 29.181us 1 1 100.00