| host_error_intr |
0 |
1 |
0.00 |
|
i2c_host_error_intr |
0.990s |
170.250us |
0 |
1 |
0.00
|
| host_stress_all |
1 |
1 |
100.00 |
|
i2c_host_stress_all |
1641.940s |
39624.363us |
1 |
1 |
100.00
|
| host_maxperf |
1 |
1 |
100.00 |
|
i2c_host_perf |
25.720s |
10837.169us |
1 |
1 |
100.00
|
| host_override |
1 |
1 |
100.00 |
|
i2c_host_override |
0.790s |
166.196us |
1 |
1 |
100.00
|
| host_fifo_watermark |
1 |
1 |
100.00 |
|
i2c_host_fifo_watermark |
50.500s |
12923.883us |
1 |
1 |
100.00
|
| host_fifo_overflow |
1 |
1 |
100.00 |
|
i2c_host_fifo_overflow |
48.820s |
4697.141us |
1 |
1 |
100.00
|
| host_fifo_reset |
3 |
3 |
100.00 |
|
i2c_host_fifo_reset_fmt |
1.360s |
1251.259us |
1 |
1 |
100.00
|
|
i2c_host_fifo_fmt_empty |
13.360s |
796.118us |
1 |
1 |
100.00
|
|
i2c_host_fifo_reset_rx |
3.200s |
180.025us |
1 |
1 |
100.00
|
| host_fifo_full |
1 |
1 |
100.00 |
|
i2c_host_fifo_full |
31.870s |
7466.569us |
1 |
1 |
100.00
|
| host_timeout |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
9.290s |
795.115us |
1 |
1 |
100.00
|
| i2c_host_mode_toggle |
0 |
1 |
0.00 |
|
i2c_host_mode_toggle |
0.960s |
26.845us |
0 |
1 |
0.00
|
| target_glitch |
0 |
1 |
0.00 |
|
i2c_target_glitch |
2.290s |
435.408us |
0 |
1 |
0.00
|
| target_stress_all |
1 |
1 |
100.00 |
|
i2c_target_stress_all |
55.200s |
41606.704us |
1 |
1 |
100.00
|
| target_maxperf |
1 |
1 |
100.00 |
|
i2c_target_perf |
3.950s |
2712.549us |
1 |
1 |
100.00
|
| target_fifo_empty |
2 |
2 |
100.00 |
|
i2c_target_stress_rd |
4.370s |
5317.950us |
1 |
1 |
100.00
|
|
i2c_target_intr_smoke |
5.480s |
854.760us |
1 |
1 |
100.00
|
| target_fifo_reset |
2 |
2 |
100.00 |
|
i2c_target_fifo_reset_acq |
1.590s |
243.694us |
1 |
1 |
100.00
|
|
i2c_target_fifo_reset_tx |
1.380s |
612.064us |
1 |
1 |
100.00
|
| target_fifo_full |
3 |
3 |
100.00 |
|
i2c_target_stress_wr |
131.600s |
61843.619us |
1 |
1 |
100.00
|
|
i2c_target_stress_rd |
4.370s |
5317.950us |
1 |
1 |
100.00
|
|
i2c_target_intr_stress_wr |
104.630s |
12136.525us |
1 |
1 |
100.00
|
| target_timeout |
1 |
1 |
100.00 |
|
i2c_target_timeout |
5.190s |
5994.912us |
1 |
1 |
100.00
|
| target_clock_stretch |
1 |
1 |
100.00 |
|
i2c_target_stretch |
9.470s |
1753.693us |
1 |
1 |
100.00
|
| bad_address |
1 |
1 |
100.00 |
|
i2c_target_bad_addr |
3.300s |
1545.738us |
1 |
1 |
100.00
|
| target_mode_glitch |
1 |
1 |
100.00 |
|
i2c_target_hrst |
2.250s |
734.229us |
1 |
1 |
100.00
|
| target_fifo_watermark |
2 |
2 |
100.00 |
|
i2c_target_fifo_watermarks_acq |
2.030s |
540.434us |
1 |
1 |
100.00
|
|
i2c_target_fifo_watermarks_tx |
1.210s |
140.901us |
1 |
1 |
100.00
|
| host_mode_config_perf |
2 |
2 |
100.00 |
|
i2c_host_perf |
25.720s |
10837.169us |
1 |
1 |
100.00
|
|
i2c_host_perf_precise |
1.210s |
132.777us |
1 |
1 |
100.00
|
| host_mode_clock_stretching |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
9.290s |
795.115us |
1 |
1 |
100.00
|
| target_mode_tx_stretch_ctrl |
1 |
1 |
100.00 |
|
i2c_target_tx_stretch_ctrl |
9.390s |
941.409us |
1 |
1 |
100.00
|
| target_mode_nack_generation |
2 |
3 |
66.67 |
|
i2c_target_nack_acqfull |
2.250s |
1580.121us |
1 |
1 |
100.00
|
|
i2c_target_nack_acqfull_addr |
2.780s |
537.224us |
1 |
1 |
100.00
|
|
i2c_target_nack_txstretch |
1.280s |
129.499us |
0 |
1 |
0.00
|
| host_mode_halt_on_nak |
1 |
1 |
100.00 |
|
i2c_host_may_nack |
18.680s |
1330.632us |
1 |
1 |
100.00
|
| target_mode_smbus_maxlen |
1 |
1 |
100.00 |
|
i2c_target_smbus_maxlen |
2.440s |
1046.326us |
1 |
1 |
100.00
|
| alert_test |
1 |
1 |
100.00 |
|
i2c_alert_test |
0.770s |
35.213us |
1 |
1 |
100.00
|
| intr_test |
1 |
1 |
100.00 |
|
i2c_intr_test |
0.770s |
19.204us |
1 |
1 |
100.00
|
| tl_d_oob_addr_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.610s |
34.080us |
1 |
1 |
100.00
|
| tl_d_illegal_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.610s |
34.080us |
1 |
1 |
100.00
|
| tl_d_outstanding_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.940s |
20.368us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.740s |
29.672us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.290s |
51.720us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
1.080s |
35.847us |
1 |
1 |
100.00
|
| tl_d_partial_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.940s |
20.368us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.740s |
29.672us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.290s |
51.720us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
1.080s |
35.847us |
1 |
1 |
100.00
|