Simulation Results: keymgr

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 90.38
  • line
  • 98.7
  • cond
  • 94.44
  • toggle
  • 97.84
  • fsm
  • 86.05
  • branch
  • 97.67
  • assert
  • 97.72
  • group
  • 60.27
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 5.250s 220.812us 1 1 100.00
random 1 1 100.00
keymgr_random 3.510s 189.617us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 0.950s 75.403us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.050s 50.827us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 5.800s 985.739us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 6.990s 454.830us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.280s 34.944us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.050s 50.827us 1 1 100.00
keymgr_csr_aliasing 6.990s 454.830us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 2.360s 154.903us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 4.740s 156.020us 1 1 100.00
keymgr_sideload_kmac 3.350s 248.886us 1 1 100.00
keymgr_sideload_aes 1.950s 65.940us 1 1 100.00
keymgr_sideload_otbn 4.150s 122.248us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 4.620s 197.988us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 2.820s 114.313us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 2.390s 93.887us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 22.670s 1477.472us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 11.500s 676.111us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 2.370s 170.518us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 398.740s 66071.578us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 1.030s 13.758us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 1.020s 11.089us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 1.830s 846.840us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 1.830s 846.840us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 0.950s 75.403us 1 1 100.00
keymgr_csr_rw 1.050s 50.827us 1 1 100.00
keymgr_csr_aliasing 6.990s 454.830us 1 1 100.00
keymgr_same_csr_outstanding 1.960s 137.220us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 0.950s 75.403us 1 1 100.00
keymgr_csr_rw 1.050s 50.827us 1 1 100.00
keymgr_csr_aliasing 6.990s 454.830us 1 1 100.00
keymgr_same_csr_outstanding 1.960s 137.220us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 4.880s 252.332us 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 4.180s 614.287us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 4.180s 614.287us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 4.180s 614.287us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 4.180s 614.287us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 3.430s 395.103us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 4.880s 252.332us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 4.180s 614.287us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 2.360s 154.903us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 1.050s 50.827us 1 1 100.00
keymgr_random 3.510s 189.617us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 1.050s 50.827us 1 1 100.00
keymgr_random 3.510s 189.617us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 1.050s 50.827us 1 1 100.00
keymgr_random 3.510s 189.617us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 2.820s 114.313us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 11.500s 676.111us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 11.500s 676.111us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 3.510s 189.617us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 2.750s 58.711us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 2.060s 210.727us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 2.820s 114.313us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.060s 210.727us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.060s 210.727us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 2.060s 210.727us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 5.030s 432.030us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 2.060s 210.727us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 4.980s 298.874us 0 1 0.00