Simulation Results: lc_ctrl

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 85.94
  • line
  • 96.97
  • cond
  • 79.14
  • toggle
  • 81.02
  • fsm
  • 69.47
  • branch
  • 93.62
  • assert
  • 94.13
  • group
  • 87.19
Validation stages
V1
100.00%
V2
85.00%
V2S
67.86%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
lc_ctrl_smoke 6.710s 1700.898us 2 2 100.00
csr_hw_reset 2 2 100.00
lc_ctrl_csr_hw_reset 1.260s 22.327us 2 2 100.00
csr_rw 2 2 100.00
lc_ctrl_csr_rw 0.890s 31.311us 2 2 100.00
csr_bit_bash 2 2 100.00
lc_ctrl_csr_bit_bash 1.570s 110.614us 2 2 100.00
csr_aliasing 2 2 100.00
lc_ctrl_csr_aliasing 1.190s 68.266us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
lc_ctrl_csr_mem_rw_with_rand_reset 1.260s 92.134us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
lc_ctrl_csr_rw 0.890s 31.311us 2 2 100.00
lc_ctrl_csr_aliasing 1.190s 68.266us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
state_post_trans 2 2 100.00
lc_ctrl_state_post_trans 6.800s 469.541us 2 2 100.00
regwen_during_op 2 2 100.00
lc_ctrl_regwen_during_op 16.300s 347.409us 2 2 100.00
rand_wr_claim_transition_if 2 2 100.00
lc_ctrl_claim_transition_if 1.160s 13.121us 2 2 100.00
lc_prog_failure 2 2 100.00
lc_ctrl_prog_failure 2.330s 147.354us 2 2 100.00
lc_state_failure 0 2 0.00
lc_ctrl_state_failure 1.240s 3.085us 0 2 0.00
lc_errors 1 2 50.00
lc_ctrl_errors 7.590s 1017.435us 1 2 50.00
security_escalation 9 14 64.29
lc_ctrl_state_failure 1.240s 3.085us 0 2 0.00
lc_ctrl_prog_failure 2.330s 147.354us 2 2 100.00
lc_ctrl_errors 7.590s 1017.435us 1 2 50.00
lc_ctrl_security_escalation 9.140s 433.126us 2 2 100.00
lc_ctrl_jtag_state_failure 7.710s 229.330us 0 2 0.00
lc_ctrl_jtag_prog_failure 11.020s 1939.926us 2 2 100.00
lc_ctrl_jtag_errors 32.410s 1611.435us 2 2 100.00
jtag_access 24 26 92.31
lc_ctrl_jtag_smoke 4.580s 176.361us 2 2 100.00
lc_ctrl_jtag_state_post_trans 12.790s 1264.739us 0 2 0.00
lc_ctrl_jtag_prog_failure 11.020s 1939.926us 2 2 100.00
lc_ctrl_jtag_errors 32.410s 1611.435us 2 2 100.00
lc_ctrl_jtag_access 6.480s 1197.676us 2 2 100.00
lc_ctrl_jtag_regwen_during_op 14.090s 5656.725us 2 2 100.00
lc_ctrl_jtag_csr_hw_reset 2.840s 199.348us 2 2 100.00
lc_ctrl_jtag_csr_rw 1.820s 369.621us 2 2 100.00
lc_ctrl_jtag_csr_bit_bash 9.580s 2224.381us 2 2 100.00
lc_ctrl_jtag_csr_aliasing 6.070s 5230.434us 2 2 100.00
lc_ctrl_jtag_same_csr_outstanding 1.800s 198.316us 2 2 100.00
lc_ctrl_jtag_csr_mem_rw_with_rand_reset 3.600s 174.209us 2 2 100.00
lc_ctrl_jtag_alert_test 1.500s 49.206us 2 2 100.00
jtag_priority 2 2 100.00
lc_ctrl_jtag_priority 8.060s 2257.425us 2 2 100.00
lc_ctrl_volatile_unlock 2 2 100.00
lc_ctrl_volatile_unlock_smoke 1.010s 53.475us 2 2 100.00
stress_all 0 2 0.00
lc_ctrl_stress_all 9.580s 2459.182us 0 2 0.00
alert_test 2 2 100.00
lc_ctrl_alert_test 1.620s 34.273us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
lc_ctrl_tl_errors 2.920s 667.654us 2 2 100.00
tl_d_illegal_access 2 2 100.00
lc_ctrl_tl_errors 2.920s 667.654us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
lc_ctrl_csr_hw_reset 1.260s 22.327us 2 2 100.00
lc_ctrl_csr_rw 0.890s 31.311us 2 2 100.00
lc_ctrl_csr_aliasing 1.190s 68.266us 2 2 100.00
lc_ctrl_same_csr_outstanding 1.850s 55.181us 2 2 100.00
tl_d_partial_access 8 8 100.00
lc_ctrl_csr_hw_reset 1.260s 22.327us 2 2 100.00
lc_ctrl_csr_rw 0.890s 31.311us 2 2 100.00
lc_ctrl_csr_aliasing 1.190s 68.266us 2 2 100.00
lc_ctrl_same_csr_outstanding 1.850s 55.181us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 4 4 100.00
lc_ctrl_sec_cm 7.410s 1017.177us 2 2 100.00
lc_ctrl_tl_intg_err 3.000s 122.794us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
lc_ctrl_tl_intg_err 3.000s 122.794us 2 2 100.00
sec_cm_transition_config_regwen 2 2 100.00
lc_ctrl_regwen_during_op 16.300s 347.409us 2 2 100.00
sec_cm_manuf_state_sparse 2 4 50.00
lc_ctrl_state_failure 1.240s 3.085us 0 2 0.00
lc_ctrl_sec_cm 7.410s 1017.177us 2 2 100.00
sec_cm_transition_ctr_sparse 2 4 50.00
lc_ctrl_state_failure 1.240s 3.085us 0 2 0.00
lc_ctrl_sec_cm 7.410s 1017.177us 2 2 100.00
sec_cm_manuf_state_bkgn_chk 2 4 50.00
lc_ctrl_state_failure 1.240s 3.085us 0 2 0.00
lc_ctrl_sec_cm 7.410s 1017.177us 2 2 100.00
sec_cm_transition_ctr_bkgn_chk 2 4 50.00
lc_ctrl_state_failure 1.240s 3.085us 0 2 0.00
lc_ctrl_sec_cm 7.410s 1017.177us 2 2 100.00
sec_cm_state_config_sparse 2 4 50.00
lc_ctrl_state_failure 1.240s 3.085us 0 2 0.00
lc_ctrl_sec_cm 7.410s 1017.177us 2 2 100.00
sec_cm_main_fsm_sparse 2 4 50.00
lc_ctrl_state_failure 1.240s 3.085us 0 2 0.00
lc_ctrl_sec_cm 7.410s 1017.177us 2 2 100.00
sec_cm_kmac_fsm_sparse 2 4 50.00
lc_ctrl_state_failure 1.240s 3.085us 0 2 0.00
lc_ctrl_sec_cm 7.410s 1017.177us 2 2 100.00
sec_cm_main_fsm_local_esc 2 4 50.00
lc_ctrl_state_failure 1.240s 3.085us 0 2 0.00
lc_ctrl_sec_cm 7.410s 1017.177us 2 2 100.00
sec_cm_main_fsm_global_esc 2 2 100.00
lc_ctrl_security_escalation 9.140s 433.126us 2 2 100.00
sec_cm_main_ctrl_flow_consistency 2 4 50.00
lc_ctrl_state_post_trans 6.800s 469.541us 2 2 100.00
lc_ctrl_jtag_state_post_trans 12.790s 1264.739us 0 2 0.00
sec_cm_intersig_mubi 2 2 100.00
lc_ctrl_sec_mubi 8.110s 421.544us 2 2 100.00
sec_cm_token_valid_ctrl_mubi 2 2 100.00
lc_ctrl_sec_mubi 8.110s 421.544us 2 2 100.00
sec_cm_token_digest 2 2 100.00
lc_ctrl_sec_token_digest 12.190s 1069.112us 2 2 100.00
sec_cm_token_mux_ctrl_redun 2 2 100.00
lc_ctrl_sec_token_mux 8.680s 1592.133us 2 2 100.00
sec_cm_token_valid_mux_redun 2 2 100.00
lc_ctrl_sec_token_mux 8.680s 1592.133us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 2 0.00
lc_ctrl_stress_all_with_rand_reset 47.830s 4506.368us 0 2 0.00