Simulation Results: pattgen

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 98.31
  • block
  • 100.0
  • branch
  • 100.0
  • statement
  • 100.0
  • expression
  • 97.0
  • toggle
  • 96.61
  • fsm
  • None
  • assertion
  • 96.95
  • covergroup
  • 89.42
Validation stages
V1
100.00%
V2
93.75%
V2S
100.00%
V3
0.00%
unmapped
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 87.331us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 15.603us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 2.000s 23.948us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 35.533us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 44.502us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 72.945us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 2.000s 23.948us 1 1 100.00
pattgen_csr_aliasing 1.000s 44.502us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 19.000s 2931.872us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 10.000s 347.651us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 469.024us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 0.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 1.000s 20.008us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 2.000s 13.098us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 333.295us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 333.295us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 15.603us 1 1 100.00
pattgen_csr_rw 2.000s 23.948us 1 1 100.00
pattgen_csr_aliasing 1.000s 44.502us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 14.604us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 15.603us 1 1 100.00
pattgen_csr_rw 2.000s 23.948us 1 1 100.00
pattgen_csr_aliasing 1.000s 44.502us 1 1 100.00
pattgen_same_csr_outstanding 1.000s 14.604us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 282.164us 1 1 100.00
pattgen_tl_intg_err 2.000s 44.940us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 44.940us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 22.000s 9829.583us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 0 1 0.00
pattgen_inactive_level 8.000s 10022.679us 0 1 0.00