Simulation Results: pwrmgr

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 94.97
  • line
  • 98.76
  • cond
  • 94.34
  • toggle
  • 90.02
  • fsm
  • 94.0
  • branch
  • 94.85
  • assert
  • 95.82
  • group
  • 97.03
Validation stages
V1
100.00%
V2
100.00%
V2S
47.06%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.940s 23.613us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.650s 83.974us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.700s 46.356us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.670s 473.990us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.720s 35.139us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.790s 51.837us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.700s 46.356us 1 1 100.00
pwrmgr_csr_aliasing 0.720s 35.139us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.770s 98.196us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.770s 98.196us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.830s 29.237us 1 1 100.00
pwrmgr_lowpower_invalid 0.740s 43.018us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.910s 86.587us 1 1 100.00
pwrmgr_reset_invalid 0.920s 102.429us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.910s 86.587us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.080s 656.400us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.570s 31.643us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.890s 55.090us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 0.760s 79.806us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.650s 20.605us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.440s 67.465us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.440s 67.465us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 83.974us 1 1 100.00
pwrmgr_csr_rw 0.700s 46.356us 1 1 100.00
pwrmgr_csr_aliasing 0.720s 35.139us 1 1 100.00
pwrmgr_same_csr_outstanding 0.730s 53.669us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.650s 83.974us 1 1 100.00
pwrmgr_csr_rw 0.700s 46.356us 1 1 100.00
pwrmgr_csr_aliasing 0.720s 35.139us 1 1 100.00
pwrmgr_same_csr_outstanding 0.730s 53.669us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.740s 7.612us 0 1 0.00
pwrmgr_tl_intg_err 0.780s 11.270us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.740s 7.612us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.740s 7.612us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.780s 11.270us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.750s 799.165us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 1.080s 656.400us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.910s 133.167us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 0 1 0.00
pwrmgr_esc_clk_rst_malfunc 0.740s 13.270us 0 1 0.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.740s 7.612us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.740s 7.612us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.740s 7.612us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.800s 24.365us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.600s 73.878us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.820s 216.158us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.700s 46.356us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.700s 46.356us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.840s 341.603us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 7.550s 7156.597us 1 1 100.00