Simulation Results: rom_ctrl

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 95.16
  • line
  • 99.32
  • cond
  • 93.31
  • toggle
  • 99.59
  • fsm
  • 86.67
  • branch
  • 97.45
  • assert
  • 95.49
  • group
  • 94.27
Validation stages
V1
100.00%
V2
100.00%
V2S
66.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 7.400s 920.005us 2 2 100.00
csr_hw_reset 2 2 100.00
rom_ctrl_csr_hw_reset 10.400s 392.206us 2 2 100.00
csr_rw 2 2 100.00
rom_ctrl_csr_rw 6.840s 1072.123us 2 2 100.00
csr_bit_bash 2 2 100.00
rom_ctrl_csr_bit_bash 7.200s 545.060us 2 2 100.00
csr_aliasing 2 2 100.00
rom_ctrl_csr_aliasing 5.790s 726.346us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.470s 395.598us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
rom_ctrl_csr_rw 6.840s 1072.123us 2 2 100.00
rom_ctrl_csr_aliasing 5.790s 726.346us 2 2 100.00
mem_walk 2 2 100.00
rom_ctrl_mem_walk 6.800s 2280.216us 2 2 100.00
mem_partial_access 2 2 100.00
rom_ctrl_mem_partial_access 7.470s 700.098us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.800s 405.011us 2 2 100.00
stress_all 2 2 100.00
rom_ctrl_stress_all 29.520s 744.876us 2 2 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 11.970s 1189.357us 2 2 100.00
alert_test 2 2 100.00
rom_ctrl_alert_test 6.310s 205.733us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
rom_ctrl_tl_errors 10.090s 299.993us 2 2 100.00
tl_d_illegal_access 2 2 100.00
rom_ctrl_tl_errors 10.090s 299.993us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
rom_ctrl_csr_hw_reset 10.400s 392.206us 2 2 100.00
rom_ctrl_csr_rw 6.840s 1072.123us 2 2 100.00
rom_ctrl_csr_aliasing 5.790s 726.346us 2 2 100.00
rom_ctrl_same_csr_outstanding 6.960s 1074.626us 2 2 100.00
tl_d_partial_access 8 8 100.00
rom_ctrl_csr_hw_reset 10.400s 392.206us 2 2 100.00
rom_ctrl_csr_rw 6.840s 1072.123us 2 2 100.00
rom_ctrl_csr_aliasing 5.790s 726.346us 2 2 100.00
rom_ctrl_same_csr_outstanding 6.960s 1074.626us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 161.350s 9902.494us 1 2 50.00
passthru_mem_tl_intg_err 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.340s 2888.744us 2 2 100.00
tl_intg_err 3 4 75.00
rom_ctrl_tl_intg_err 51.370s 1217.242us 2 2 100.00
rom_ctrl_sec_cm 485.970s 22301.128us 1 2 50.00
prim_fsm_check 1 2 50.00
rom_ctrl_sec_cm 485.970s 22301.128us 1 2 50.00
prim_count_check 1 2 50.00
rom_ctrl_sec_cm 485.970s 22301.128us 1 2 50.00
sec_cm_checker_ctr_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 161.350s 9902.494us 1 2 50.00
sec_cm_checker_ctrl_flow_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 161.350s 9902.494us 1 2 50.00
sec_cm_checker_fsm_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 161.350s 9902.494us 1 2 50.00
sec_cm_compare_ctrl_flow_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 161.350s 9902.494us 1 2 50.00
sec_cm_compare_ctr_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 161.350s 9902.494us 1 2 50.00
sec_cm_compare_ctr_redun 1 2 50.00
rom_ctrl_sec_cm 485.970s 22301.128us 1 2 50.00
sec_cm_fsm_sparse 1 2 50.00
rom_ctrl_sec_cm 485.970s 22301.128us 1 2 50.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 7.400s 920.005us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 7.400s 920.005us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 7.400s 920.005us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
rom_ctrl_tl_intg_err 51.370s 1217.242us 2 2 100.00
sec_cm_bus_local_esc 3 4 75.00
rom_ctrl_corrupt_sig_fatal_chk 161.350s 9902.494us 1 2 50.00
rom_ctrl_kmac_err_chk 11.970s 1189.357us 2 2 100.00
sec_cm_mux_mubi 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 161.350s 9902.494us 1 2 50.00
sec_cm_mux_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 161.350s 9902.494us 1 2 50.00
sec_cm_ctrl_redun 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 161.350s 9902.494us 1 2 50.00
sec_cm_ctrl_mem_integrity 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 23.340s 2888.744us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 1 2 50.00
rom_ctrl_sec_cm 485.970s 22301.128us 1 2 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
rom_ctrl_stress_all_with_rand_reset 100.510s 3754.021us 2 2 100.00