Simulation Results: rstmgr

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 98.53
  • line
  • 99.51
  • cond
  • 98.61
  • toggle
  • 98.99
  • fsm
  • None
  • branch
  • 99.83
  • assert
  • 97.72
  • group
  • 96.52
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.430s 206.371us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 1.050s 147.108us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 1.040s 66.445us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 4.050s 1180.503us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.630s 195.654us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 0.970s 122.246us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 1.040s 66.445us 1 1 100.00
rstmgr_csr_aliasing 1.630s 195.654us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.900s 160.985us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 2.220s 476.735us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 1.040s 104.772us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 3.260s 783.947us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 3.260s 783.947us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 3.260s 783.947us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 3.260s 783.947us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 21.670s 8128.931us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.830s 84.859us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 2.590s 411.493us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 2.590s 411.493us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 1.050s 147.108us 1 1 100.00
rstmgr_csr_rw 1.040s 66.445us 1 1 100.00
rstmgr_csr_aliasing 1.630s 195.654us 1 1 100.00
rstmgr_same_csr_outstanding 1.400s 267.985us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 1.050s 147.108us 1 1 100.00
rstmgr_csr_rw 1.040s 66.445us 1 1 100.00
rstmgr_csr_aliasing 1.630s 195.654us 1 1 100.00
rstmgr_same_csr_outstanding 1.400s 267.985us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 11.970s 8444.355us 1 1 100.00
rstmgr_tl_intg_err 1.930s 493.118us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 11.970s 8444.355us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 11.970s 8444.355us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 1.930s 493.118us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 1.150s 92.909us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.950s 2446.416us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.030s 304.903us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 11.970s 8444.355us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 1.040s 66.445us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 1.040s 66.445us 1 1 100.00