Simulation Results: rv_dm

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 75.63
  • line
  • 93.82
  • cond
  • 83.63
  • toggle
  • 70.86
  • fsm
  • 71.43
  • branch
  • 85.0
  • assert
  • 95.31
  • group
  • 29.35
Validation stages
V1
96.77%
V2
67.86%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 4.340s 2663.810us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 2.880s 697.752us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 1.080s 154.085us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 2.560s 4316.355us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 1.910s 1174.974us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 3.240s 2535.357us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 5.920s 2809.377us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 13.280s 23613.174us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 33.840s 18172.084us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 1.100s 293.261us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 1.230s 200.413us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 0.890s 347.729us 1 1 100.00
mem_tl_access_resuming 1 1 100.00
rv_dm_mem_tl_access_resuming 2.040s 282.415us 1 1 100.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 0.870s 96.761us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 1.520s 1815.190us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 1.150s 190.050us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 1.020s 742.113us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 1.100s 293.261us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 1.200s 266.188us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.290s 472.810us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 0.890s 347.729us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 0.950s 113.325us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 2.150s 268.877us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.730s 159.743us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 46.390s 4927.238us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 22.770s 13694.889us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 0.930s 47.045us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 22.770s 13694.889us 1 1 100.00
rv_dm_csr_rw 1.730s 159.743us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.760s 52.618us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.670s 33.847us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 4.340s 2663.810us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 1.370s 130.619us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.920s 166.478us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 1.000s 291.311us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 2.960s 1039.976us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 137.740s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 287.790s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 45.590s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 528.630s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 1 1 100.00
rv_dm_jtag_dmi_debug_disabled 1.040s 127.163us 1 1 100.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 1.950s 1935.526us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 1.310s 303.326us 1 1 100.00
hart_unavail 1 1 100.00
rv_dm_hart_unavail 0.940s 148.600us 1 1 100.00
tap_ctrl_transitions 0 2 0.00
rv_dm_tap_fsm_rand_reset 0.780s 74.046us 0 1 0.00
rv_dm_tap_fsm 35.670s 21682.479us 0 1 0.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.840s 69.588us 1 1 100.00
stress_all 0 1 0.00
rv_dm_stress_all 9.900s 10917.339us 0 1 0.00
alert_test 1 1 100.00
rv_dm_alert_test 0.990s 128.938us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rv_dm_tl_errors 1.050s 119.212us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rv_dm_tl_errors 1.050s 119.212us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 22.770s 13694.889us 1 1 100.00
rv_dm_csr_hw_reset 2.150s 268.877us 1 1 100.00
rv_dm_csr_rw 1.730s 159.743us 1 1 100.00
rv_dm_same_csr_outstanding 3.220s 295.009us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 22.770s 13694.889us 1 1 100.00
rv_dm_csr_hw_reset 2.150s 268.877us 1 1 100.00
rv_dm_csr_rw 1.730s 159.743us 1 1 100.00
rv_dm_same_csr_outstanding 3.220s 295.009us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 12.270s 2891.674us 1 1 100.00
rv_dm_sec_cm 2.020s 407.425us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 12.270s 2891.674us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 1.950s 1935.526us 1 1 100.00
rv_dm_debug_disabled 1.000s 116.351us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 1.950s 1935.526us 1 1 100.00
rv_dm_debug_disabled 1.000s 116.351us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 4.340s 2663.810us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 0.920s 213.679us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.860s 74.720us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 0.860s 74.720us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 0.920s 213.679us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 1.020s 27.510us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
rv_dm_scanmode 0.700s 40.382us 1 1 100.00