Simulation Results: spi_device

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 91.76
  • line
  • 99.17
  • cond
  • 96.22
  • toggle
  • 87.74
  • fsm
  • 89.36
  • branch
  • 98.47
  • assert
  • 94.27
  • group
  • 77.08
Validation stages
V1
100.00%
V2
98.08%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
spi_device_flash_and_tpm 234.630s 42225.293us 2 2 100.00
csr_hw_reset 2 2 100.00
spi_device_csr_hw_reset 1.270s 203.402us 2 2 100.00
csr_rw 2 2 100.00
spi_device_csr_rw 1.730s 284.695us 2 2 100.00
csr_bit_bash 2 2 100.00
spi_device_csr_bit_bash 15.960s 1463.559us 2 2 100.00
csr_aliasing 2 2 100.00
spi_device_csr_aliasing 10.170s 1396.458us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
spi_device_csr_mem_rw_with_rand_reset 2.220s 429.765us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
spi_device_csr_rw 1.730s 284.695us 2 2 100.00
spi_device_csr_aliasing 10.170s 1396.458us 2 2 100.00
mem_walk 2 2 100.00
spi_device_mem_walk 0.950s 13.000us 2 2 100.00
mem_partial_access 2 2 100.00
spi_device_mem_partial_access 1.710s 128.645us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 2 2 100.00
spi_device_csb_read 1.000s 20.814us 2 2 100.00
mem_parity 1 2 50.00
spi_device_mem_parity 0.930s 15.672us 1 2 50.00
mem_cfg 1 2 50.00
spi_device_ram_cfg 0.850s 4.856us 1 2 50.00
tpm_read 2 2 100.00
spi_device_tpm_rw 2.090s 65.107us 2 2 100.00
tpm_write 2 2 100.00
spi_device_tpm_rw 2.090s 65.107us 2 2 100.00
tpm_hw_reg 4 4 100.00
spi_device_tpm_read_hw_reg 10.660s 52471.412us 2 2 100.00
spi_device_tpm_sts_read 1.110s 82.846us 2 2 100.00
tpm_fully_random_case 2 2 100.00
spi_device_tpm_all 16.270s 16694.962us 2 2 100.00
pass_cmd_filtering 4 4 100.00
spi_device_pass_cmd_filtering 2.690s 143.611us 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
pass_addr_translation 4 4 100.00
spi_device_pass_addr_payload_swap 16.050s 8695.963us 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
pass_payload_translation 4 4 100.00
spi_device_pass_addr_payload_swap 16.050s 8695.963us 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
cmd_info_slots 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
cmd_read_status 4 4 100.00
spi_device_intercept 5.700s 7113.026us 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
cmd_read_jedec 4 4 100.00
spi_device_intercept 5.700s 7113.026us 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
cmd_read_sfdp 4 4 100.00
spi_device_intercept 5.700s 7113.026us 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
cmd_fast_read 4 4 100.00
spi_device_intercept 5.700s 7113.026us 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
cmd_read_pipeline 4 4 100.00
spi_device_intercept 5.700s 7113.026us 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
flash_cmd_upload 2 2 100.00
spi_device_upload 6.120s 1416.107us 2 2 100.00
mailbox_command 2 2 100.00
spi_device_mailbox 22.460s 23548.813us 2 2 100.00
mailbox_cross_outside_command 2 2 100.00
spi_device_mailbox 22.460s 23548.813us 2 2 100.00
mailbox_cross_inside_command 2 2 100.00
spi_device_mailbox 22.460s 23548.813us 2 2 100.00
cmd_read_buffer 4 4 100.00
spi_device_flash_mode 51.270s 19592.937us 2 2 100.00
spi_device_read_buffer_direct 5.800s 3375.860us 2 2 100.00
cmd_dummy_cycle 4 4 100.00
spi_device_mailbox 22.460s 23548.813us 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
quad_spi 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
dual_spi 2 2 100.00
spi_device_flash_all 234.180s 53064.756us 2 2 100.00
4b_3b_feature 2 2 100.00
spi_device_cfg_cmd 2.940s 907.755us 2 2 100.00
write_enable_disable 2 2 100.00
spi_device_cfg_cmd 2.940s 907.755us 2 2 100.00
TPM_with_flash_or_passthrough_mode 2 2 100.00
spi_device_flash_and_tpm 234.630s 42225.293us 2 2 100.00
tpm_and_flash_trans_with_min_inactive_time 2 2 100.00
spi_device_flash_and_tpm_min_idle 79.840s 14637.148us 2 2 100.00
stress_all 2 2 100.00
spi_device_stress_all 352.280s 140338.400us 2 2 100.00
alert_test 2 2 100.00
spi_device_alert_test 0.810s 13.999us 2 2 100.00
intr_test 2 2 100.00
spi_device_intr_test 0.990s 15.154us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
spi_device_tl_errors 3.050s 251.141us 2 2 100.00
tl_d_illegal_access 2 2 100.00
spi_device_tl_errors 3.050s 251.141us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
spi_device_csr_hw_reset 1.270s 203.402us 2 2 100.00
spi_device_csr_rw 1.730s 284.695us 2 2 100.00
spi_device_csr_aliasing 10.170s 1396.458us 2 2 100.00
spi_device_same_csr_outstanding 2.730s 142.368us 2 2 100.00
tl_d_partial_access 8 8 100.00
spi_device_csr_hw_reset 1.270s 203.402us 2 2 100.00
spi_device_csr_rw 1.730s 284.695us 2 2 100.00
spi_device_csr_aliasing 10.170s 1396.458us 2 2 100.00
spi_device_same_csr_outstanding 2.730s 142.368us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 4 4 100.00
spi_device_tl_intg_err 13.320s 292.598us 2 2 100.00
spi_device_sec_cm 1.440s 353.290us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
spi_device_tl_intg_err 13.320s 292.598us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 2 100.00
spi_device_flash_mode_ignore_cmds 165.280s 38563.248us 2 2 100.00