Simulation Results: sram_ctrl

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 92.5
  • line
  • 97.86
  • cond
  • 91.92
  • toggle
  • 90.53
  • fsm
  • 80.95
  • branch
  • 95.45
  • assert
  • 95.79
  • group
  • 94.99
Validation stages
V1
100.00%
V2
100.00%
V2S
72.92%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
sram_ctrl_smoke 9.340s 1112.675us 2 2 100.00
csr_hw_reset 2 2 100.00
sram_ctrl_csr_hw_reset 0.820s 14.866us 2 2 100.00
csr_rw 2 2 100.00
sram_ctrl_csr_rw 0.850s 13.428us 2 2 100.00
csr_bit_bash 2 2 100.00
sram_ctrl_csr_bit_bash 1.430s 42.172us 2 2 100.00
csr_aliasing 2 2 100.00
sram_ctrl_csr_aliasing 0.750s 12.590us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.220s 343.547us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
sram_ctrl_csr_rw 0.850s 13.428us 2 2 100.00
sram_ctrl_csr_aliasing 0.750s 12.590us 2 2 100.00
mem_walk 2 2 100.00
sram_ctrl_mem_walk 238.660s 55294.388us 2 2 100.00
mem_partial_access 2 2 100.00
sram_ctrl_mem_partial_access 122.230s 23138.844us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 2 2 100.00
sram_ctrl_multiple_keys 508.800s 77940.790us 2 2 100.00
stress_pipeline 2 2 100.00
sram_ctrl_stress_pipeline 224.200s 4852.452us 2 2 100.00
bijection 2 2 100.00
sram_ctrl_bijection 845.080s 229778.054us 2 2 100.00
access_during_key_req 2 2 100.00
sram_ctrl_access_during_key_req 266.970s 7586.228us 2 2 100.00
lc_escalation 2 2 100.00
sram_ctrl_lc_escalation 6.290s 1495.112us 2 2 100.00
executable 2 2 100.00
sram_ctrl_executable 169.970s 41139.220us 2 2 100.00
partial_access 4 4 100.00
sram_ctrl_partial_access 24.370s 419.411us 2 2 100.00
sram_ctrl_partial_access_b2b 358.240s 17812.990us 2 2 100.00
max_throughput 6 6 100.00
sram_ctrl_max_throughput 49.700s 535.450us 2 2 100.00
sram_ctrl_throughput_w_partial_write 52.380s 550.980us 2 2 100.00
sram_ctrl_throughput_w_readback 12.910s 770.040us 2 2 100.00
regwen 2 2 100.00
sram_ctrl_regwen 317.220s 7523.387us 2 2 100.00
ram_cfg 2 2 100.00
sram_ctrl_ram_cfg 3.440s 1347.422us 2 2 100.00
stress_all 2 2 100.00
sram_ctrl_stress_all 581.360s 33347.354us 2 2 100.00
alert_test 2 2 100.00
sram_ctrl_alert_test 0.940s 10.927us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
sram_ctrl_tl_errors 2.730s 433.805us 2 2 100.00
tl_d_illegal_access 2 2 100.00
sram_ctrl_tl_errors 2.730s 433.805us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.820s 14.866us 2 2 100.00
sram_ctrl_csr_rw 0.850s 13.428us 2 2 100.00
sram_ctrl_csr_aliasing 0.750s 12.590us 2 2 100.00
sram_ctrl_same_csr_outstanding 0.810s 13.471us 2 2 100.00
tl_d_partial_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.820s 14.866us 2 2 100.00
sram_ctrl_csr_rw 0.850s 13.428us 2 2 100.00
sram_ctrl_csr_aliasing 0.750s 12.590us 2 2 100.00
sram_ctrl_same_csr_outstanding 0.810s 13.471us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 32.800s 27180.146us 2 2 100.00
tl_intg_err 2 4 50.00
sram_ctrl_tl_intg_err 1.870s 367.614us 2 2 100.00
sram_ctrl_sec_cm 0.950s 4.085us 0 2 0.00
prim_count_check 0 2 0.00
sram_ctrl_sec_cm 0.950s 4.085us 0 2 0.00
sec_cm_bus_integrity 2 2 100.00
sram_ctrl_tl_intg_err 1.870s 367.614us 2 2 100.00
sec_cm_ctrl_config_regwen 2 2 100.00
sram_ctrl_regwen 317.220s 7523.387us 2 2 100.00
sec_cm_readback_config_regwen 2 2 100.00
sram_ctrl_regwen 317.220s 7523.387us 2 2 100.00
sec_cm_exec_config_regwen 2 2 100.00
sram_ctrl_csr_rw 0.850s 13.428us 2 2 100.00
sec_cm_exec_config_mubi 2 2 100.00
sram_ctrl_executable 169.970s 41139.220us 2 2 100.00
sec_cm_exec_intersig_mubi 2 2 100.00
sram_ctrl_executable 169.970s 41139.220us 2 2 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
sram_ctrl_executable 169.970s 41139.220us 2 2 100.00
sec_cm_lc_escalate_en_intersig_mubi 2 2 100.00
sram_ctrl_lc_escalation 6.290s 1495.112us 2 2 100.00
sec_cm_prim_ram_ctrl_mubi 1 2 50.00
sram_ctrl_mubi_enc_err 4.480s 1424.979us 1 2 50.00
sec_cm_mem_integrity 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 32.800s 27180.146us 2 2 100.00
sec_cm_mem_readback 2 2 100.00
sram_ctrl_readback_err 3.740s 2640.042us 2 2 100.00
sec_cm_mem_scramble 2 2 100.00
sram_ctrl_smoke 9.340s 1112.675us 2 2 100.00
sec_cm_addr_scramble 2 2 100.00
sram_ctrl_smoke 9.340s 1112.675us 2 2 100.00
sec_cm_instr_bus_lc_gated 2 2 100.00
sram_ctrl_executable 169.970s 41139.220us 2 2 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 2 0.00
sram_ctrl_sec_cm 0.950s 4.085us 0 2 0.00
sec_cm_key_global_esc 2 2 100.00
sram_ctrl_lc_escalation 6.290s 1495.112us 2 2 100.00
sec_cm_key_local_esc 0 2 0.00
sram_ctrl_sec_cm 0.950s 4.085us 0 2 0.00
sec_cm_init_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.950s 4.085us 0 2 0.00
sec_cm_scramble_key_sideload 2 2 100.00
sram_ctrl_smoke 9.340s 1112.675us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.950s 4.085us 0 2 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
sram_ctrl_stress_all_with_rand_reset 104.860s 12381.151us 2 2 100.00