Simulation Results: sysrst_ctrl

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 85.86
  • line
  • 95.22
  • cond
  • 92.52
  • toggle
  • 99.77
  • fsm
  • 63.46
  • branch
  • 96.07
  • assert
  • 88.6
  • group
  • 65.38
Validation stages
V1
100.00%
V2
95.65%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 2.050s 2121.834us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 4.670s 2461.272us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.630s 2408.115us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 6.630s 2542.458us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 3.500s 6095.663us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.600s 2127.882us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 73.580s 38770.773us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 6.760s 2743.343us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 5.110s 2064.203us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.600s 2127.882us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.760s 2743.343us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 15.920s 31043.469us 1 1 100.00
combo_detect_with_pre_cond 0 1 0.00
sysrst_ctrl_combo_detect_with_pre_cond 42.730s 24143.521us 0 1 0.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 4.240s 3527.066us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 1.140s 3067.527us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.140s 2509.377us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.330s 2205.159us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 7.260s 3456.023us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 6.400s 2609.536us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 1.750s 4623.654us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 3.570s 30666.206us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 18.420s 9528.807us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 5.290s 2012.372us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 2.650s 2018.132us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 2.990s 2114.383us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 2.990s 2114.383us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.500s 6095.663us 1 1 100.00
sysrst_ctrl_csr_rw 1.600s 2127.882us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.760s 2743.343us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 25.470s 9478.415us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 3.500s 6095.663us 1 1 100.00
sysrst_ctrl_csr_rw 1.600s 2127.882us 1 1 100.00
sysrst_ctrl_csr_aliasing 6.760s 2743.343us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 25.470s 9478.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 16.030s 42186.684us 1 1 100.00
sysrst_ctrl_tl_intg_err 80.000s 42399.325us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 80.000s 42399.325us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 12.060s 6218.969us 1 1 100.00