Simulation Results: uart

 
18/11/2025 19:24:33 sha: 7662858 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 90.19
  • line
  • 99.17
  • cond
  • 95.22
  • toggle
  • 91.55
  • fsm
  • None
  • branch
  • 97.44
  • assert
  • 97.12
  • group
  • 60.63
Validation stages
V1
100.00%
V2
97.06%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.700s 453.750us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.610s 19.696us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.610s 14.097us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.810s 60.956us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.930s 20.600us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 1.040s 25.154us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.610s 14.097us 1 1 100.00
uart_csr_aliasing 0.930s 20.600us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 38.920s 138609.143us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.700s 453.750us 1 1 100.00
uart_tx_rx 38.920s 138609.143us 1 1 100.00
parity_error 2 2 100.00
uart_intr 12.750s 10152.164us 1 1 100.00
uart_rx_parity_err 28.950s 65177.109us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 38.920s 138609.143us 1 1 100.00
uart_intr 12.750s 10152.164us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 21.610s 188381.567us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 42.640s 152960.184us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 33.200s 28368.988us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 12.750s 10152.164us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 12.750s 10152.164us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 12.750s 10152.164us 1 1 100.00
perf 1 1 100.00
uart_perf 588.970s 32334.048us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 6.500s 11674.610us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 6.500s 11674.610us 1 1 100.00
rx_noise_filter 0 1 0.00
uart_noise_filter 12.110s 11209.728us 0 1 0.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 27.160s 24458.483us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.160s 983.822us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 10.930s 7640.010us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 935.120s 168265.749us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 327.150s 195660.199us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.590s 15.320us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.760s 13.820us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.150s 138.926us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.150s 138.926us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.610s 19.696us 1 1 100.00
uart_csr_rw 0.610s 14.097us 1 1 100.00
uart_csr_aliasing 0.930s 20.600us 1 1 100.00
uart_same_csr_outstanding 0.720s 21.711us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.610s 19.696us 1 1 100.00
uart_csr_rw 0.610s 14.097us 1 1 100.00
uart_csr_aliasing 0.930s 20.600us 1 1 100.00
uart_same_csr_outstanding 0.720s 21.711us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 1.060s 32.817us 1 1 100.00
uart_tl_intg_err 0.890s 54.916us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.890s 54.916us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 5.590s 1607.452us 1 1 100.00