Simulation Results: adc_ctrl

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 90.23
  • line
  • 99.05
  • cond
  • 95.66
  • toggle
  • 100.0
  • fsm
  • 91.89
  • branch
  • 98.58
  • assert
  • 95.62
  • group
  • 50.79
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 10.540s 5973.631us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 2.450s 1078.977us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 0.940s 639.256us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 3.080s 3633.651us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.280s 1616.682us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 0.810s 602.933us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 0.940s 639.256us 1 1 100.00
adc_ctrl_csr_aliasing 1.280s 1616.682us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 192.150s 166072.814us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 433.440s 321915.150us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 86.550s 494293.054us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 747.290s 487852.851us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 239.980s 599126.279us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 170.180s 205160.254us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 932.340s 516445.794us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 176.870s 2000000.000us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 3.170s 2930.400us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 40.040s 25319.826us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 19.690s 81477.181us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 929.920s 537042.444us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 0.850s 526.986us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.440s 470.021us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.210s 616.823us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.210s 616.823us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.450s 1078.977us 1 1 100.00
adc_ctrl_csr_rw 0.940s 639.256us 1 1 100.00
adc_ctrl_csr_aliasing 1.280s 1616.682us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.610s 2439.360us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 2.450s 1078.977us 1 1 100.00
adc_ctrl_csr_rw 0.940s 639.256us 1 1 100.00
adc_ctrl_csr_aliasing 1.280s 1616.682us 1 1 100.00
adc_ctrl_same_csr_outstanding 1.610s 2439.360us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_sec_cm 3.750s 7557.065us 1 1 100.00
adc_ctrl_tl_intg_err 5.270s 8730.714us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 5.270s 8730.714us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 10.820s 7785.305us 1 1 100.00