Simulation Results: edn

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 86.36
  • line
  • 98.36
  • cond
  • 88.4
  • toggle
  • 94.49
  • fsm
  • 53.49
  • branch
  • 94.57
  • assert
  • 97.56
  • group
  • 77.67
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 0.880s 38.935us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 0.790s 164.453us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.790s 19.893us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 4.220s 259.273us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 1.210s 43.873us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 0.980s 37.942us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.790s 19.893us 1 1 100.00
edn_csr_aliasing 1.210s 43.873us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.070s 69.423us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.070s 69.423us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.070s 69.423us 1 1 100.00
interrupts 1 1 100.00
edn_intr 0.880s 31.766us 1 1 100.00
alerts 1 1 100.00
edn_alert 0.920s 24.002us 1 1 100.00
errs 1 1 100.00
edn_err 0.820s 28.060us 1 1 100.00
disable 2 2 100.00
edn_disable 0.780s 13.807us 1 1 100.00
edn_disable_auto_req_mode 0.930s 34.512us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 0.920s 35.262us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.760s 19.727us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 0.750s 15.823us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 2.850s 110.886us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 2.850s 110.886us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 0.790s 164.453us 1 1 100.00
edn_csr_rw 0.790s 19.893us 1 1 100.00
edn_csr_aliasing 1.210s 43.873us 1 1 100.00
edn_same_csr_outstanding 0.970s 69.849us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 0.790s 164.453us 1 1 100.00
edn_csr_rw 0.790s 19.893us 1 1 100.00
edn_csr_aliasing 1.210s 43.873us 1 1 100.00
edn_same_csr_outstanding 0.970s 69.849us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_sec_cm 3.620s 1084.860us 1 1 100.00
edn_tl_intg_err 1.940s 100.953us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 0.860s 53.964us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 0.920s 24.002us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.620s 1084.860us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 3.620s 1084.860us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 3.620s 1084.860us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 3.620s 1084.860us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 0.920s 24.002us 1 1 100.00
edn_sec_cm 3.620s 1084.860us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 0.920s 24.002us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.940s 100.953us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
edn_stress_all_with_rand_reset 33.630s 15901.336us 1 1 100.00