Simulation Results: hmac

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.82
  • line
  • 99.74
  • cond
  • 95.84
  • toggle
  • 100.0
  • fsm
  • 94.12
  • branch
  • 99.01
  • assert
  • 96.42
  • group
  • 43.64
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 8.700s 895.750us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.780s 21.026us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.830s 14.374us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.690s 734.200us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 3.970s 107.303us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.140s 62.959us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.830s 14.374us 1 1 100.00
hmac_csr_aliasing 3.970s 107.303us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 48.900s 2029.297us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 2.080s 49.368us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 9.270s 334.073us 1 1 100.00
hmac_test_sha384_vectors 22.250s 4606.030us 1 1 100.00
hmac_test_sha512_vectors 23.460s 450.651us 1 1 100.00
hmac_test_hmac256_vectors 8.880s 512.038us 1 1 100.00
hmac_test_hmac384_vectors 8.280s 971.457us 1 1 100.00
hmac_test_hmac512_vectors 9.710s 1110.874us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 18.640s 2915.136us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 819.060s 12597.358us 1 1 100.00
error 1 1 100.00
hmac_error 33.470s 4281.977us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 51.180s 1389.596us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 8.700s 895.750us 1 1 100.00
hmac_long_msg 48.900s 2029.297us 1 1 100.00
hmac_back_pressure 2.080s 49.368us 1 1 100.00
hmac_datapath_stress 819.060s 12597.358us 1 1 100.00
hmac_burst_wr 18.640s 2915.136us 1 1 100.00
hmac_stress_all 564.770s 88394.344us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 8.700s 895.750us 1 1 100.00
hmac_long_msg 48.900s 2029.297us 1 1 100.00
hmac_back_pressure 2.080s 49.368us 1 1 100.00
hmac_datapath_stress 819.060s 12597.358us 1 1 100.00
hmac_wipe_secret 51.180s 1389.596us 1 1 100.00
hmac_test_sha256_vectors 9.270s 334.073us 1 1 100.00
hmac_test_sha384_vectors 22.250s 4606.030us 1 1 100.00
hmac_test_sha512_vectors 23.460s 450.651us 1 1 100.00
hmac_test_hmac256_vectors 8.880s 512.038us 1 1 100.00
hmac_test_hmac384_vectors 8.280s 971.457us 1 1 100.00
hmac_test_hmac512_vectors 9.710s 1110.874us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 8.700s 895.750us 1 1 100.00
hmac_long_msg 48.900s 2029.297us 1 1 100.00
hmac_back_pressure 2.080s 49.368us 1 1 100.00
hmac_datapath_stress 819.060s 12597.358us 1 1 100.00
hmac_burst_wr 18.640s 2915.136us 1 1 100.00
hmac_error 33.470s 4281.977us 1 1 100.00
hmac_wipe_secret 51.180s 1389.596us 1 1 100.00
hmac_test_sha256_vectors 9.270s 334.073us 1 1 100.00
hmac_test_sha384_vectors 22.250s 4606.030us 1 1 100.00
hmac_test_sha512_vectors 23.460s 450.651us 1 1 100.00
hmac_test_hmac256_vectors 8.880s 512.038us 1 1 100.00
hmac_test_hmac384_vectors 8.280s 971.457us 1 1 100.00
hmac_test_hmac512_vectors 9.710s 1110.874us 1 1 100.00
hmac_stress_all 564.770s 88394.344us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 564.770s 88394.344us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.700s 12.177us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.730s 12.186us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 3.070s 80.218us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 3.070s 80.218us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.780s 21.026us 1 1 100.00
hmac_csr_rw 0.830s 14.374us 1 1 100.00
hmac_csr_aliasing 3.970s 107.303us 1 1 100.00
hmac_same_csr_outstanding 1.420s 52.402us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.780s 21.026us 1 1 100.00
hmac_csr_rw 0.830s 14.374us 1 1 100.00
hmac_csr_aliasing 3.970s 107.303us 1 1 100.00
hmac_same_csr_outstanding 1.420s 52.402us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 1.490s 99.365us 1 1 100.00
hmac_sec_cm 1.030s 57.966us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.490s 99.365us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 8.700s 895.750us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 1.430s 45.076us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 38.190s 5821.103us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 3.640s 204.112us 1 1 100.00