| host_error_intr |
0 |
1 |
0.00 |
|
i2c_host_error_intr |
0.960s |
5.858us |
0 |
1 |
0.00
|
| host_stress_all |
1 |
1 |
100.00 |
|
i2c_host_stress_all |
181.490s |
17396.799us |
1 |
1 |
100.00
|
| host_maxperf |
1 |
1 |
100.00 |
|
i2c_host_perf |
3.410s |
195.664us |
1 |
1 |
100.00
|
| host_override |
1 |
1 |
100.00 |
|
i2c_host_override |
0.980s |
19.895us |
1 |
1 |
100.00
|
| host_fifo_watermark |
1 |
1 |
100.00 |
|
i2c_host_fifo_watermark |
113.630s |
31079.713us |
1 |
1 |
100.00
|
| host_fifo_overflow |
1 |
1 |
100.00 |
|
i2c_host_fifo_overflow |
96.510s |
2224.102us |
1 |
1 |
100.00
|
| host_fifo_reset |
3 |
3 |
100.00 |
|
i2c_host_fifo_reset_fmt |
1.180s |
161.674us |
1 |
1 |
100.00
|
|
i2c_host_fifo_fmt_empty |
2.050s |
2417.037us |
1 |
1 |
100.00
|
|
i2c_host_fifo_reset_rx |
6.060s |
481.657us |
1 |
1 |
100.00
|
| host_fifo_full |
1 |
1 |
100.00 |
|
i2c_host_fifo_full |
48.760s |
13262.738us |
1 |
1 |
100.00
|
| host_timeout |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
12.500s |
843.916us |
1 |
1 |
100.00
|
| i2c_host_mode_toggle |
0 |
1 |
0.00 |
|
i2c_host_mode_toggle |
1.700s |
93.813us |
0 |
1 |
0.00
|
| target_glitch |
0 |
1 |
0.00 |
|
i2c_target_glitch |
4.030s |
957.613us |
0 |
1 |
0.00
|
| target_stress_all |
1 |
1 |
100.00 |
|
i2c_target_stress_all |
74.350s |
99567.939us |
1 |
1 |
100.00
|
| target_maxperf |
1 |
1 |
100.00 |
|
i2c_target_perf |
4.430s |
3348.284us |
1 |
1 |
100.00
|
| target_fifo_empty |
2 |
2 |
100.00 |
|
i2c_target_stress_rd |
5.200s |
449.616us |
1 |
1 |
100.00
|
|
i2c_target_intr_smoke |
4.530s |
5251.984us |
1 |
1 |
100.00
|
| target_fifo_reset |
2 |
2 |
100.00 |
|
i2c_target_fifo_reset_acq |
1.120s |
380.850us |
1 |
1 |
100.00
|
|
i2c_target_fifo_reset_tx |
1.230s |
182.388us |
1 |
1 |
100.00
|
| target_fifo_full |
3 |
3 |
100.00 |
|
i2c_target_stress_wr |
3.470s |
16500.370us |
1 |
1 |
100.00
|
|
i2c_target_stress_rd |
5.200s |
449.616us |
1 |
1 |
100.00
|
|
i2c_target_intr_stress_wr |
108.870s |
24194.785us |
1 |
1 |
100.00
|
| target_timeout |
1 |
1 |
100.00 |
|
i2c_target_timeout |
4.760s |
1032.772us |
1 |
1 |
100.00
|
| target_clock_stretch |
1 |
1 |
100.00 |
|
i2c_target_stretch |
5.100s |
4839.907us |
1 |
1 |
100.00
|
| bad_address |
1 |
1 |
100.00 |
|
i2c_target_bad_addr |
2.340s |
482.781us |
1 |
1 |
100.00
|
| target_mode_glitch |
0 |
1 |
0.00 |
|
i2c_target_hrst |
5.420s |
10582.974us |
0 |
1 |
0.00
|
| target_fifo_watermark |
2 |
2 |
100.00 |
|
i2c_target_fifo_watermarks_acq |
2.430s |
10519.665us |
1 |
1 |
100.00
|
|
i2c_target_fifo_watermarks_tx |
1.280s |
259.435us |
1 |
1 |
100.00
|
| host_mode_config_perf |
2 |
2 |
100.00 |
|
i2c_host_perf |
3.410s |
195.664us |
1 |
1 |
100.00
|
|
i2c_host_perf_precise |
2.160s |
87.511us |
1 |
1 |
100.00
|
| host_mode_clock_stretching |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
12.500s |
843.916us |
1 |
1 |
100.00
|
| target_mode_tx_stretch_ctrl |
1 |
1 |
100.00 |
|
i2c_target_tx_stretch_ctrl |
7.730s |
756.628us |
1 |
1 |
100.00
|
| target_mode_nack_generation |
2 |
3 |
66.67 |
|
i2c_target_nack_acqfull |
2.520s |
2638.005us |
1 |
1 |
100.00
|
|
i2c_target_nack_acqfull_addr |
2.110s |
477.926us |
1 |
1 |
100.00
|
|
i2c_target_nack_txstretch |
1.580s |
910.494us |
0 |
1 |
0.00
|
| host_mode_halt_on_nak |
1 |
1 |
100.00 |
|
i2c_host_may_nack |
3.780s |
1007.899us |
1 |
1 |
100.00
|
| target_mode_smbus_maxlen |
1 |
1 |
100.00 |
|
i2c_target_smbus_maxlen |
1.820s |
806.538us |
1 |
1 |
100.00
|
| alert_test |
1 |
1 |
100.00 |
|
i2c_alert_test |
0.710s |
16.150us |
1 |
1 |
100.00
|
| intr_test |
1 |
1 |
100.00 |
|
i2c_intr_test |
0.940s |
44.255us |
1 |
1 |
100.00
|
| tl_d_oob_addr_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.940s |
129.393us |
1 |
1 |
100.00
|
| tl_d_illegal_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
1.940s |
129.393us |
1 |
1 |
100.00
|
| tl_d_outstanding_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.760s |
75.010us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.880s |
114.738us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.540s |
133.775us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
1.110s |
314.239us |
1 |
1 |
100.00
|
| tl_d_partial_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.760s |
75.010us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.880s |
114.738us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.540s |
133.775us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
1.110s |
314.239us |
1 |
1 |
100.00
|