Simulation Results: keymgr

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 91.26
  • line
  • 98.74
  • cond
  • 94.51
  • toggle
  • 97.66
  • fsm
  • 88.37
  • branch
  • 97.94
  • assert
  • 97.49
  • group
  • 64.12
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
keymgr_smoke 2.140s 81.179us 1 1 100.00
random 1 1 100.00
keymgr_random 4.300s 192.456us 1 1 100.00
csr_hw_reset 1 1 100.00
keymgr_csr_hw_reset 1.050s 148.734us 1 1 100.00
csr_rw 1 1 100.00
keymgr_csr_rw 1.170s 80.405us 1 1 100.00
csr_bit_bash 1 1 100.00
keymgr_csr_bit_bash 10.310s 263.749us 1 1 100.00
csr_aliasing 1 1 100.00
keymgr_csr_aliasing 3.520s 276.646us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
keymgr_csr_mem_rw_with_rand_reset 1.300s 70.245us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
keymgr_csr_rw 1.170s 80.405us 1 1 100.00
keymgr_csr_aliasing 3.520s 276.646us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
cfgen_during_op 1 1 100.00
keymgr_cfg_regwen 2.690s 175.304us 1 1 100.00
sideload 4 4 100.00
keymgr_sideload 2.250s 250.203us 1 1 100.00
keymgr_sideload_kmac 2.430s 235.359us 1 1 100.00
keymgr_sideload_aes 1.930s 34.715us 1 1 100.00
keymgr_sideload_otbn 15.380s 780.396us 1 1 100.00
direct_to_disabled_state 1 1 100.00
keymgr_direct_to_disabled 3.130s 118.135us 1 1 100.00
lc_disable 1 1 100.00
keymgr_lc_disable 1.860s 164.518us 1 1 100.00
kmac_error_response 1 1 100.00
keymgr_kmac_rsp_err 3.120s 125.252us 1 1 100.00
invalid_sw_input 1 1 100.00
keymgr_sw_invalid_input 4.090s 142.799us 1 1 100.00
invalid_hw_input 1 1 100.00
keymgr_hwsw_invalid_input 2.670s 58.678us 1 1 100.00
sync_async_fault_cross 1 1 100.00
keymgr_sync_async_fault_cross 1.250s 355.794us 1 1 100.00
stress_all 1 1 100.00
keymgr_stress_all 24.970s 1508.645us 1 1 100.00
intr_test 1 1 100.00
keymgr_intr_test 0.720s 51.526us 1 1 100.00
alert_test 1 1 100.00
keymgr_alert_test 0.700s 8.681us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
keymgr_tl_errors 2.620s 141.316us 1 1 100.00
tl_d_illegal_access 1 1 100.00
keymgr_tl_errors 2.620s 141.316us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
keymgr_csr_hw_reset 1.050s 148.734us 1 1 100.00
keymgr_csr_rw 1.170s 80.405us 1 1 100.00
keymgr_csr_aliasing 3.520s 276.646us 1 1 100.00
keymgr_same_csr_outstanding 3.870s 118.269us 1 1 100.00
tl_d_partial_access 4 4 100.00
keymgr_csr_hw_reset 1.050s 148.734us 1 1 100.00
keymgr_csr_rw 1.170s 80.405us 1 1 100.00
keymgr_csr_aliasing 3.520s 276.646us 1 1 100.00
keymgr_same_csr_outstanding 3.870s 118.269us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
sec_cm_additional_check 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
tl_intg_err 2 2 100.00
keymgr_tl_intg_err 7.040s 468.280us 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
shadow_reg_update_error 1 1 100.00
keymgr_shadow_reg_errors 4.460s 242.316us 1 1 100.00
shadow_reg_read_clear_staged_value 1 1 100.00
keymgr_shadow_reg_errors 4.460s 242.316us 1 1 100.00
shadow_reg_storage_error 1 1 100.00
keymgr_shadow_reg_errors 4.460s 242.316us 1 1 100.00
shadowed_reset_glitch 1 1 100.00
keymgr_shadow_reg_errors 4.460s 242.316us 1 1 100.00
shadow_reg_update_error_with_csr_rw 1 1 100.00
keymgr_shadow_reg_errors_with_csr_rw 13.660s 565.527us 1 1 100.00
prim_count_check 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
prim_fsm_check 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
keymgr_tl_intg_err 7.040s 468.280us 1 1 100.00
sec_cm_config_shadow 1 1 100.00
keymgr_shadow_reg_errors 4.460s 242.316us 1 1 100.00
sec_cm_op_config_regwen 1 1 100.00
keymgr_cfg_regwen 2.690s 175.304us 1 1 100.00
sec_cm_reseed_config_regwen 2 2 100.00
keymgr_csr_rw 1.170s 80.405us 1 1 100.00
keymgr_random 4.300s 192.456us 1 1 100.00
sec_cm_sw_binding_config_regwen 2 2 100.00
keymgr_csr_rw 1.170s 80.405us 1 1 100.00
keymgr_random 4.300s 192.456us 1 1 100.00
sec_cm_max_key_ver_config_regwen 2 2 100.00
keymgr_csr_rw 1.170s 80.405us 1 1 100.00
keymgr_random 4.300s 192.456us 1 1 100.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
keymgr_lc_disable 1.860s 164.518us 1 1 100.00
sec_cm_constants_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.670s 58.678us 1 1 100.00
sec_cm_intersig_consistency 1 1 100.00
keymgr_hwsw_invalid_input 2.670s 58.678us 1 1 100.00
sec_cm_hw_key_sw_noaccess 1 1 100.00
keymgr_random 4.300s 192.456us 1 1 100.00
sec_cm_output_keys_ctrl_redun 1 1 100.00
keymgr_sideload_protect 11.360s 2439.832us 1 1 100.00
sec_cm_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
sec_cm_data_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
sec_cm_ctrl_fsm_local_esc 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
sec_cm_ctrl_fsm_consistency 1 1 100.00
keymgr_custom_cm 3.840s 532.403us 1 1 100.00
sec_cm_ctrl_fsm_global_esc 1 1 100.00
keymgr_lc_disable 1.860s 164.518us 1 1 100.00
sec_cm_ctrl_ctr_redun 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
sec_cm_kmac_if_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
sec_cm_kmac_if_ctr_redun 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
sec_cm_kmac_if_cmd_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.840s 532.403us 1 1 100.00
sec_cm_kmac_if_done_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.840s 532.403us 1 1 100.00
sec_cm_reseed_ctr_redun 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
sec_cm_side_load_sel_ctrl_consistency 1 1 100.00
keymgr_custom_cm 3.840s 532.403us 1 1 100.00
sec_cm_sideload_ctrl_fsm_sparse 1 1 100.00
keymgr_sec_cm 10.570s 1505.490us 1 1 100.00
sec_cm_ctrl_key_integrity 1 1 100.00
keymgr_custom_cm 3.840s 532.403us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
keymgr_stress_all_with_rand_reset 3.490s 233.206us 0 1 0.00