Simulation Results: pattgen

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 98.36
  • block
  • 100.0
  • branch
  • 100.0
  • statement
  • 100.0
  • expression
  • 97.75
  • toggle
  • 96.61
  • fsm
  • None
  • assertion
  • 96.65
  • covergroup
  • 88.94
Validation stages
V1
100.00%
V2
87.50%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 2.000s 21.066us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 2.000s 24.272us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 33.367us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 2.000s 34.355us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 2.000s 13.415us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 1.000s 92.427us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 33.367us 1 1 100.00
pattgen_csr_aliasing 2.000s 13.415us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 0 1 0.00
pattgen_perf 361.000s 600000.000us 0 1 0.00
cnt_rollover 1 1 100.00
cnt_rollover 66.000s 2743.529us 1 1 100.00
error 1 1 100.00
pattgen_error 1.000s 79.834us 1 1 100.00
stress_all 0 1 0.00
pattgen_stress_all 0.000s 0.000us 0 1 0.00
alert_test 1 1 100.00
pattgen_alert_test 2.000s 12.565us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 2.000s 19.138us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 65.169us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 65.169us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 24.272us 1 1 100.00
pattgen_csr_rw 1.000s 33.367us 1 1 100.00
pattgen_csr_aliasing 2.000s 13.415us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 102.895us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 2.000s 24.272us 1 1 100.00
pattgen_csr_rw 1.000s 33.367us 1 1 100.00
pattgen_csr_aliasing 2.000s 13.415us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 102.895us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 2.000s 259.189us 1 1 100.00
pattgen_tl_intg_err 1.000s 91.879us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 1.000s 91.879us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 12.000s 1096.138us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 69.576us 1 1 100.00