Simulation Results: pwrmgr

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 95.15
  • line
  • 98.92
  • cond
  • 93.92
  • toggle
  • 90.02
  • fsm
  • 94.0
  • branch
  • 95.42
  • assert
  • 96.08
  • group
  • 97.69
Validation stages
V1
100.00%
V2
100.00%
V2S
52.94%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.650s 30.484us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.640s 88.896us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.590s 51.072us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 2.420s 781.339us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.870s 162.602us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.810s 134.631us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.590s 51.072us 1 1 100.00
pwrmgr_csr_aliasing 0.870s 162.602us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.820s 251.556us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.820s 251.556us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.620s 162.565us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 46.016us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.750s 22.767us 1 1 100.00
pwrmgr_reset_invalid 0.860s 94.527us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.750s 22.767us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 1.100s 299.602us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.690s 97.209us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 0.690s 103.283us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 2.230s 1641.906us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.640s 22.688us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.290s 35.100us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.290s 35.100us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.640s 88.896us 1 1 100.00
pwrmgr_csr_rw 0.590s 51.072us 1 1 100.00
pwrmgr_csr_aliasing 0.870s 162.602us 1 1 100.00
pwrmgr_same_csr_outstanding 0.760s 120.265us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.640s 88.896us 1 1 100.00
pwrmgr_csr_rw 0.590s 51.072us 1 1 100.00
pwrmgr_csr_aliasing 0.870s 162.602us 1 1 100.00
pwrmgr_same_csr_outstanding 0.760s 120.265us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.670s 32.699us 0 1 0.00
pwrmgr_tl_intg_err 0.680s 10.302us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.670s 32.699us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.670s 32.699us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.680s 10.302us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 2.070s 805.130us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 1.100s 299.602us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.780s 47.743us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.600s 41.495us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.670s 32.699us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.670s 32.699us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.670s 32.699us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.600s 96.881us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.680s 56.326us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.700s 138.422us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 51.072us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.590s 51.072us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.760s 110.176us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 4.590s 1686.609us 1 1 100.00