Simulation Results: rom_ctrl

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 96.61
  • line
  • 99.32
  • cond
  • 94.65
  • toggle
  • 98.5
  • fsm
  • 93.33
  • branch
  • 98.54
  • assert
  • 95.49
  • group
  • 96.42
Validation stages
V1
100.00%
V2
100.00%
V2S
75.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.950s 874.753us 2 2 100.00
csr_hw_reset 2 2 100.00
rom_ctrl_csr_hw_reset 10.510s 400.642us 2 2 100.00
csr_rw 2 2 100.00
rom_ctrl_csr_rw 5.590s 1410.719us 2 2 100.00
csr_bit_bash 2 2 100.00
rom_ctrl_csr_bit_bash 6.440s 726.819us 2 2 100.00
csr_aliasing 2 2 100.00
rom_ctrl_csr_aliasing 7.300s 1218.339us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 7.110s 218.881us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
rom_ctrl_csr_rw 5.590s 1410.719us 2 2 100.00
rom_ctrl_csr_aliasing 7.300s 1218.339us 2 2 100.00
mem_walk 2 2 100.00
rom_ctrl_mem_walk 5.630s 727.297us 2 2 100.00
mem_partial_access 2 2 100.00
rom_ctrl_mem_partial_access 7.120s 4159.313us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.680s 416.062us 2 2 100.00
stress_all 2 2 100.00
rom_ctrl_stress_all 28.310s 2107.398us 2 2 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 15.390s 549.982us 2 2 100.00
alert_test 2 2 100.00
rom_ctrl_alert_test 6.320s 376.864us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
rom_ctrl_tl_errors 7.640s 725.796us 2 2 100.00
tl_d_illegal_access 2 2 100.00
rom_ctrl_tl_errors 7.640s 725.796us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
rom_ctrl_csr_hw_reset 10.510s 400.642us 2 2 100.00
rom_ctrl_csr_rw 5.590s 1410.719us 2 2 100.00
rom_ctrl_csr_aliasing 7.300s 1218.339us 2 2 100.00
rom_ctrl_same_csr_outstanding 9.930s 319.174us 2 2 100.00
tl_d_partial_access 8 8 100.00
rom_ctrl_csr_hw_reset 10.510s 400.642us 2 2 100.00
rom_ctrl_csr_rw 5.590s 1410.719us 2 2 100.00
rom_ctrl_csr_aliasing 7.300s 1218.339us 2 2 100.00
rom_ctrl_same_csr_outstanding 9.930s 319.174us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.650s 7082.323us 2 2 100.00
passthru_mem_tl_intg_err 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.700s 2679.586us 2 2 100.00
tl_intg_err 2 4 50.00
rom_ctrl_sec_cm 232.030s 1442.912us 0 2 0.00
rom_ctrl_tl_intg_err 101.040s 1790.419us 2 2 100.00
prim_fsm_check 0 2 0.00
rom_ctrl_sec_cm 232.030s 1442.912us 0 2 0.00
prim_count_check 0 2 0.00
rom_ctrl_sec_cm 232.030s 1442.912us 0 2 0.00
sec_cm_checker_ctr_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.650s 7082.323us 2 2 100.00
sec_cm_checker_ctrl_flow_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.650s 7082.323us 2 2 100.00
sec_cm_checker_fsm_local_esc 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.650s 7082.323us 2 2 100.00
sec_cm_compare_ctrl_flow_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.650s 7082.323us 2 2 100.00
sec_cm_compare_ctr_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.650s 7082.323us 2 2 100.00
sec_cm_compare_ctr_redun 0 2 0.00
rom_ctrl_sec_cm 232.030s 1442.912us 0 2 0.00
sec_cm_fsm_sparse 0 2 0.00
rom_ctrl_sec_cm 232.030s 1442.912us 0 2 0.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.950s 874.753us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.950s 874.753us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.950s 874.753us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
rom_ctrl_tl_intg_err 101.040s 1790.419us 2 2 100.00
sec_cm_bus_local_esc 4 4 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.650s 7082.323us 2 2 100.00
rom_ctrl_kmac_err_chk 15.390s 549.982us 2 2 100.00
sec_cm_mux_mubi 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.650s 7082.323us 2 2 100.00
sec_cm_mux_consistency 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.650s 7082.323us 2 2 100.00
sec_cm_ctrl_redun 2 2 100.00
rom_ctrl_corrupt_sig_fatal_chk 119.650s 7082.323us 2 2 100.00
sec_cm_ctrl_mem_integrity 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 33.700s 2679.586us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 0 2 0.00
rom_ctrl_sec_cm 232.030s 1442.912us 0 2 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
rom_ctrl_stress_all_with_rand_reset 90.020s 11471.024us 2 2 100.00