Simulation Results: rstmgr

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 98.34
  • line
  • 99.51
  • cond
  • 98.68
  • toggle
  • 99.16
  • fsm
  • None
  • branch
  • 99.83
  • assert
  • 97.59
  • group
  • 95.27
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rstmgr_smoke 1.210s 257.664us 1 1 100.00
csr_hw_reset 1 1 100.00
rstmgr_csr_hw_reset 0.800s 131.080us 1 1 100.00
csr_rw 1 1 100.00
rstmgr_csr_rw 0.700s 64.276us 1 1 100.00
csr_bit_bash 1 1 100.00
rstmgr_csr_bit_bash 6.260s 1538.664us 1 1 100.00
csr_aliasing 1 1 100.00
rstmgr_csr_aliasing 1.280s 203.117us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
rstmgr_csr_mem_rw_with_rand_reset 1.300s 215.417us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rstmgr_csr_rw 0.700s 64.276us 1 1 100.00
rstmgr_csr_aliasing 1.280s 203.117us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
reset_stretcher 1 1 100.00
rstmgr_por_stretcher 0.720s 87.826us 1 1 100.00
sw_rst 1 1 100.00
rstmgr_sw_rst 1.200s 127.274us 1 1 100.00
sw_rst_reset_race 1 1 100.00
rstmgr_sw_rst_reset_race 0.870s 98.738us 1 1 100.00
reset_info 1 1 100.00
rstmgr_reset 4.040s 1480.468us 1 1 100.00
cpu_info 1 1 100.00
rstmgr_reset 4.040s 1480.468us 1 1 100.00
alert_info 1 1 100.00
rstmgr_reset 4.040s 1480.468us 1 1 100.00
reset_info_capture 1 1 100.00
rstmgr_reset 4.040s 1480.468us 1 1 100.00
stress_all 1 1 100.00
rstmgr_stress_all 26.250s 11660.165us 1 1 100.00
alert_test 1 1 100.00
rstmgr_alert_test 0.720s 69.859us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
rstmgr_tl_errors 1.550s 253.991us 1 1 100.00
tl_d_illegal_access 1 1 100.00
rstmgr_tl_errors 1.550s 253.991us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
rstmgr_csr_hw_reset 0.800s 131.080us 1 1 100.00
rstmgr_csr_rw 0.700s 64.276us 1 1 100.00
rstmgr_csr_aliasing 1.280s 203.117us 1 1 100.00
rstmgr_same_csr_outstanding 0.930s 149.282us 1 1 100.00
tl_d_partial_access 4 4 100.00
rstmgr_csr_hw_reset 0.800s 131.080us 1 1 100.00
rstmgr_csr_rw 0.700s 64.276us 1 1 100.00
rstmgr_csr_aliasing 1.280s 203.117us 1 1 100.00
rstmgr_same_csr_outstanding 0.930s 149.282us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rstmgr_sec_cm 12.570s 8414.479us 1 1 100.00
rstmgr_tl_intg_err 2.670s 897.572us 1 1 100.00
prim_count_check 1 1 100.00
rstmgr_sec_cm 12.570s 8414.479us 1 1 100.00
prim_fsm_check 1 1 100.00
rstmgr_sec_cm 12.570s 8414.479us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rstmgr_tl_intg_err 2.670s 897.572us 1 1 100.00
sec_cm_scan_intersig_mubi 1 1 100.00
rstmgr_sec_cm_scan_intersig_mubi 0.840s 107.163us 1 1 100.00
sec_cm_leaf_rst_bkgn_chk 1 1 100.00
rstmgr_leaf_rst_cnsty 5.700s 2254.889us 1 1 100.00
sec_cm_leaf_rst_shadow 1 1 100.00
rstmgr_leaf_rst_shadow_attack 1.000s 302.490us 1 1 100.00
sec_cm_leaf_fsm_sparse 1 1 100.00
rstmgr_sec_cm 12.570s 8414.479us 1 1 100.00
sec_cm_sw_rst_config_regwen 1 1 100.00
rstmgr_csr_rw 0.700s 64.276us 1 1 100.00
sec_cm_dump_ctrl_config_regwen 1 1 100.00
rstmgr_csr_rw 0.700s 64.276us 1 1 100.00