Simulation Results: rv_dm

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 77.3
  • line
  • 94.14
  • cond
  • 82.8
  • toggle
  • 69.31
  • fsm
  • 74.03
  • branch
  • 84.31
  • assert
  • 95.23
  • group
  • 41.27
Validation stages
V1
96.77%
V2
71.43%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
rv_dm_smoke 1.340s 421.051us 1 1 100.00
jtag_dtm_csr_hw_reset 1 1 100.00
rv_dm_jtag_dtm_csr_hw_reset 0.840s 540.211us 1 1 100.00
jtag_dtm_csr_rw 1 1 100.00
rv_dm_jtag_dtm_csr_rw 0.940s 214.642us 1 1 100.00
jtag_dtm_csr_bit_bash 1 1 100.00
rv_dm_jtag_dtm_csr_bit_bash 15.930s 28639.784us 1 1 100.00
jtag_dtm_csr_aliasing 1 1 100.00
rv_dm_jtag_dtm_csr_aliasing 1.340s 1211.765us 1 1 100.00
jtag_dmi_csr_hw_reset 1 1 100.00
rv_dm_jtag_dmi_csr_hw_reset 3.320s 4592.763us 1 1 100.00
jtag_dmi_csr_rw 1 1 100.00
rv_dm_jtag_dmi_csr_rw 3.340s 4205.988us 1 1 100.00
jtag_dmi_csr_bit_bash 1 1 100.00
rv_dm_jtag_dmi_csr_bit_bash 2.150s 4125.325us 1 1 100.00
jtag_dmi_csr_aliasing 1 1 100.00
rv_dm_jtag_dmi_csr_aliasing 32.380s 97323.270us 1 1 100.00
jtag_dmi_cmderr_busy 1 1 100.00
rv_dm_cmderr_busy 1.090s 618.790us 1 1 100.00
jtag_dmi_cmderr_not_supported 1 1 100.00
rv_dm_cmderr_not_supported 0.750s 165.191us 1 1 100.00
cmderr_exception 1 1 100.00
rv_dm_cmderr_exception 0.810s 176.280us 1 1 100.00
mem_tl_access_resuming 1 1 100.00
rv_dm_mem_tl_access_resuming 1.540s 384.117us 1 1 100.00
mem_tl_access_halted 1 1 100.00
rv_dm_mem_tl_access_halted 1.430s 596.982us 1 1 100.00
cmderr_halt_resume 1 1 100.00
rv_dm_cmderr_halt_resume 0.850s 519.233us 1 1 100.00
dataaddr_rw_access 1 1 100.00
rv_dm_dataaddr_rw_access 1.080s 160.003us 1 1 100.00
halt_resume 1 1 100.00
rv_dm_halt_resume_whereto 2.720s 869.703us 1 1 100.00
progbuf_busy 1 1 100.00
rv_dm_cmderr_busy 1.090s 618.790us 1 1 100.00
abstractcmd_status 1 1 100.00
rv_dm_abstractcmd_status 0.950s 151.499us 1 1 100.00
progbuf_read_write_execute 1 1 100.00
rv_dm_progbuf_read_write_execute 1.350s 523.971us 1 1 100.00
progbuf_exception 1 1 100.00
rv_dm_cmderr_exception 0.810s 176.280us 1 1 100.00
rom_read_access 1 1 100.00
rv_dm_rom_read_access 1.020s 99.934us 1 1 100.00
csr_hw_reset 1 1 100.00
rv_dm_csr_hw_reset 2.140s 270.904us 1 1 100.00
csr_rw 1 1 100.00
rv_dm_csr_rw 1.980s 121.708us 1 1 100.00
csr_bit_bash 1 1 100.00
rv_dm_csr_bit_bash 52.090s 7587.844us 1 1 100.00
csr_aliasing 1 1 100.00
rv_dm_csr_aliasing 50.650s 7719.276us 1 1 100.00
csr_mem_rw_with_rand_reset 0 1 0.00
rv_dm_csr_mem_rw_with_rand_reset 1.030s 39.588us 0 1 0.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
rv_dm_csr_aliasing 50.650s 7719.276us 1 1 100.00
rv_dm_csr_rw 1.980s 121.708us 1 1 100.00
mem_walk 1 1 100.00
rv_dm_mem_walk 0.900s 35.025us 1 1 100.00
mem_partial_access 1 1 100.00
rv_dm_mem_partial_access 0.860s 67.785us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
idcode 1 1 100.00
rv_dm_smoke 1.340s 421.051us 1 1 100.00
jtag_dtm_hard_reset 1 1 100.00
rv_dm_jtag_dtm_hard_reset 1.270s 138.900us 1 1 100.00
jtag_dtm_idle_hint 1 1 100.00
rv_dm_jtag_dtm_idle_hint 0.980s 166.790us 1 1 100.00
jtag_dmi_failed_op 1 1 100.00
rv_dm_dmi_failed_op 0.880s 116.539us 1 1 100.00
jtag_dmi_dm_inactive 1 1 100.00
rv_dm_jtag_dmi_dm_inactive 0.940s 470.679us 1 1 100.00
sba 0 2 0.00
rv_dm_sba_tl_access 448.650s 300000.000us 0 1 0.00
rv_dm_delayed_resp_sba_tl_access 273.940s 300000.000us 0 1 0.00
bad_sba 0 1 0.00
rv_dm_bad_sba_tl_access 476.200s 300000.000us 0 1 0.00
sba_autoincrement 0 1 0.00
rv_dm_autoincr_sba_tl_access 156.000s 300000.000us 0 1 0.00
jtag_dmi_debug_disabled 1 1 100.00
rv_dm_jtag_dmi_debug_disabled 1.050s 188.526us 1 1 100.00
sba_debug_disabled 1 1 100.00
rv_dm_sba_debug_disabled 1.530s 661.026us 1 1 100.00
ndmreset_req 1 1 100.00
rv_dm_ndmreset_req 1.030s 163.201us 1 1 100.00
hart_unavail 1 1 100.00
rv_dm_hart_unavail 1.290s 189.770us 1 1 100.00
tap_ctrl_transitions 0 2 0.00
rv_dm_tap_fsm_rand_reset 1.180s 163.474us 0 1 0.00
rv_dm_tap_fsm 3.660s 11083.257us 0 1 0.00
hartsel_warl 1 1 100.00
rv_dm_hartsel_warl 0.760s 155.973us 1 1 100.00
stress_all 1 1 100.00
rv_dm_stress_all 1.980s 1400.746us 1 1 100.00
alert_test 1 1 100.00
rv_dm_alert_test 0.750s 76.122us 1 1 100.00
tl_d_oob_addr_access 0 1 0.00
rv_dm_tl_errors 1.030s 40.630us 0 1 0.00
tl_d_illegal_access 0 1 0.00
rv_dm_tl_errors 1.030s 40.630us 0 1 0.00
tl_d_outstanding_access 4 4 100.00
rv_dm_csr_aliasing 50.650s 7719.276us 1 1 100.00
rv_dm_csr_hw_reset 2.140s 270.904us 1 1 100.00
rv_dm_csr_rw 1.980s 121.708us 1 1 100.00
rv_dm_same_csr_outstanding 6.180s 463.652us 1 1 100.00
tl_d_partial_access 4 4 100.00
rv_dm_csr_aliasing 50.650s 7719.276us 1 1 100.00
rv_dm_csr_hw_reset 2.140s 270.904us 1 1 100.00
rv_dm_csr_rw 1.980s 121.708us 1 1 100.00
rv_dm_same_csr_outstanding 6.180s 463.652us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
rv_dm_tl_intg_err 9.250s 1638.486us 1 1 100.00
rv_dm_sec_cm 1.960s 2607.844us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
rv_dm_tl_intg_err 9.250s 1638.486us 1 1 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 1.530s 661.026us 1 1 100.00
rv_dm_debug_disabled 0.890s 133.079us 1 1 100.00
sec_cm_lc_dft_en_intersig_mubi 2 2 100.00
rv_dm_sba_debug_disabled 1.530s 661.026us 1 1 100.00
rv_dm_debug_disabled 0.890s 133.079us 1 1 100.00
sec_cm_otp_dis_rv_dm_late_debug_intersig_mubi 1 1 100.00
rv_dm_smoke 1.340s 421.051us 1 1 100.00
sec_cm_dm_en_ctrl_lc_gated 1 1 100.00
rv_dm_buffered_enable 1.190s 242.377us 1 1 100.00
sec_cm_sba_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 1.250s 255.852us 1 1 100.00
sec_cm_mem_tl_lc_gate_fsm_sparse 1 1 100.00
rv_dm_sparse_lc_gate_fsm 1.250s 255.852us 1 1 100.00
sec_cm_exec_ctrl_mubi 1 1 100.00
rv_dm_buffered_enable 1.190s 242.377us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
rv_dm_stress_all_with_rand_reset 0.840s 14.417us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
rv_dm_scanmode 0.840s 36.937us 1 1 100.00