Simulation Results: spi_device

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 91.97
  • line
  • 99.17
  • cond
  • 96.24
  • toggle
  • 87.74
  • fsm
  • 89.36
  • branch
  • 98.47
  • assert
  • 94.27
  • group
  • 78.52
Validation stages
V1
100.00%
V2
98.08%
V2S
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
spi_device_flash_and_tpm 115.360s 223340.526us 2 2 100.00
csr_hw_reset 2 2 100.00
spi_device_csr_hw_reset 1.120s 78.800us 2 2 100.00
csr_rw 2 2 100.00
spi_device_csr_rw 1.990s 168.719us 2 2 100.00
csr_bit_bash 2 2 100.00
spi_device_csr_bit_bash 23.300s 548.700us 2 2 100.00
csr_aliasing 2 2 100.00
spi_device_csr_aliasing 13.880s 385.658us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
spi_device_csr_mem_rw_with_rand_reset 2.920s 341.366us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
spi_device_csr_rw 1.990s 168.719us 2 2 100.00
spi_device_csr_aliasing 13.880s 385.658us 2 2 100.00
mem_walk 2 2 100.00
spi_device_mem_walk 0.660s 33.164us 2 2 100.00
mem_partial_access 2 2 100.00
spi_device_mem_partial_access 1.510s 33.255us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
csb_read 2 2 100.00
spi_device_csb_read 1.130s 15.156us 2 2 100.00
mem_parity 1 2 50.00
spi_device_mem_parity 1.150s 311.876us 1 2 50.00
mem_cfg 1 2 50.00
spi_device_ram_cfg 0.720s 20.105us 1 2 50.00
tpm_read 2 2 100.00
spi_device_tpm_rw 1.190s 1288.857us 2 2 100.00
tpm_write 2 2 100.00
spi_device_tpm_rw 1.190s 1288.857us 2 2 100.00
tpm_hw_reg 4 4 100.00
spi_device_tpm_read_hw_reg 2.650s 3242.198us 2 2 100.00
spi_device_tpm_sts_read 1.340s 380.971us 2 2 100.00
tpm_fully_random_case 2 2 100.00
spi_device_tpm_all 24.790s 6037.452us 2 2 100.00
pass_cmd_filtering 4 4 100.00
spi_device_pass_cmd_filtering 7.290s 5678.726us 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
pass_addr_translation 4 4 100.00
spi_device_pass_addr_payload_swap 12.750s 5090.941us 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
pass_payload_translation 4 4 100.00
spi_device_pass_addr_payload_swap 12.750s 5090.941us 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
cmd_info_slots 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
cmd_read_status 4 4 100.00
spi_device_intercept 5.220s 708.220us 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
cmd_read_jedec 4 4 100.00
spi_device_intercept 5.220s 708.220us 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
cmd_read_sfdp 4 4 100.00
spi_device_intercept 5.220s 708.220us 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
cmd_fast_read 4 4 100.00
spi_device_intercept 5.220s 708.220us 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
cmd_read_pipeline 4 4 100.00
spi_device_intercept 5.220s 708.220us 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
flash_cmd_upload 2 2 100.00
spi_device_upload 13.120s 10782.720us 2 2 100.00
mailbox_command 2 2 100.00
spi_device_mailbox 31.530s 26581.814us 2 2 100.00
mailbox_cross_outside_command 2 2 100.00
spi_device_mailbox 31.530s 26581.814us 2 2 100.00
mailbox_cross_inside_command 2 2 100.00
spi_device_mailbox 31.530s 26581.814us 2 2 100.00
cmd_read_buffer 4 4 100.00
spi_device_flash_mode 8.980s 1297.372us 2 2 100.00
spi_device_read_buffer_direct 5.150s 1015.665us 2 2 100.00
cmd_dummy_cycle 4 4 100.00
spi_device_mailbox 31.530s 26581.814us 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
quad_spi 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
dual_spi 2 2 100.00
spi_device_flash_all 43.930s 10272.722us 2 2 100.00
4b_3b_feature 2 2 100.00
spi_device_cfg_cmd 2.270s 175.126us 2 2 100.00
write_enable_disable 2 2 100.00
spi_device_cfg_cmd 2.270s 175.126us 2 2 100.00
TPM_with_flash_or_passthrough_mode 2 2 100.00
spi_device_flash_and_tpm 115.360s 223340.526us 2 2 100.00
tpm_and_flash_trans_with_min_inactive_time 2 2 100.00
spi_device_flash_and_tpm_min_idle 501.760s 179679.532us 2 2 100.00
stress_all 2 2 100.00
spi_device_stress_all 358.320s 58303.412us 2 2 100.00
alert_test 2 2 100.00
spi_device_alert_test 0.710s 17.335us 2 2 100.00
intr_test 2 2 100.00
spi_device_intr_test 0.700s 10.690us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
spi_device_tl_errors 3.820s 809.620us 2 2 100.00
tl_d_illegal_access 2 2 100.00
spi_device_tl_errors 3.820s 809.620us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
spi_device_csr_hw_reset 1.120s 78.800us 2 2 100.00
spi_device_csr_rw 1.990s 168.719us 2 2 100.00
spi_device_csr_aliasing 13.880s 385.658us 2 2 100.00
spi_device_same_csr_outstanding 1.900s 118.694us 2 2 100.00
tl_d_partial_access 8 8 100.00
spi_device_csr_hw_reset 1.120s 78.800us 2 2 100.00
spi_device_csr_rw 1.990s 168.719us 2 2 100.00
spi_device_csr_aliasing 13.880s 385.658us 2 2 100.00
spi_device_same_csr_outstanding 1.900s 118.694us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 4 4 100.00
spi_device_tl_intg_err 5.740s 297.983us 2 2 100.00
spi_device_sec_cm 1.200s 97.472us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
spi_device_tl_intg_err 5.740s 297.983us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 2 2 100.00
spi_device_flash_mode_ignore_cmds 47.960s 7259.537us 2 2 100.00