| V1 |
|
100.00% |
| V2 |
|
100.00% |
| V2S |
|
100.00% |
| unmapped |
|
100.00% |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| smoke | 1 | 1 | 100.00 | |||
| spi_host_smoke | 34.000s | 3781.107us | 1 | 1 | 100.00 | |
| csr_hw_reset | 1 | 1 | 100.00 | |||
| spi_host_csr_hw_reset | 1.000s | 29.276us | 1 | 1 | 100.00 | |
| csr_rw | 1 | 1 | 100.00 | |||
| spi_host_csr_rw | 2.000s | 31.160us | 1 | 1 | 100.00 | |
| csr_bit_bash | 1 | 1 | 100.00 | |||
| spi_host_csr_bit_bash | 3.000s | 154.126us | 1 | 1 | 100.00 | |
| csr_aliasing | 1 | 1 | 100.00 | |||
| spi_host_csr_aliasing | 2.000s | 170.579us | 1 | 1 | 100.00 | |
| csr_mem_rw_with_rand_reset | 1 | 1 | 100.00 | |||
| spi_host_csr_mem_rw_with_rand_reset | 2.000s | 45.578us | 1 | 1 | 100.00 | |
| regwen_csr_and_corresponding_lockable_csr | 2 | 2 | 100.00 | |||
| spi_host_csr_rw | 2.000s | 31.160us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 2.000s | 170.579us | 1 | 1 | 100.00 | |
| mem_walk | 1 | 1 | 100.00 | |||
| spi_host_mem_walk | 2.000s | 15.164us | 1 | 1 | 100.00 | |
| mem_partial_access | 1 | 1 | 100.00 | |||
| spi_host_mem_partial_access | 1.000s | 111.245us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| performance | 1 | 1 | 100.00 | |||
| spi_host_performance | 9.000s | 22.368us | 1 | 1 | 100.00 | |
| error_event_intr | 3 | 3 | 100.00 | |||
| spi_host_overflow_underflow | 2.000s | 176.403us | 1 | 1 | 100.00 | |
| spi_host_error_cmd | 2.000s | 33.746us | 1 | 1 | 100.00 | |
| spi_host_event | 22.000s | 3728.227us | 1 | 1 | 100.00 | |
| clock_rate | 1 | 1 | 100.00 | |||
| spi_host_speed | 13.000s | 130.545us | 1 | 1 | 100.00 | |
| speed | 1 | 1 | 100.00 | |||
| spi_host_speed | 13.000s | 130.545us | 1 | 1 | 100.00 | |
| chip_select_timing | 1 | 1 | 100.00 | |||
| spi_host_speed | 13.000s | 130.545us | 1 | 1 | 100.00 | |
| sw_reset | 1 | 1 | 100.00 | |||
| spi_host_sw_reset | 120.000s | 7908.204us | 1 | 1 | 100.00 | |
| passthrough_mode | 1 | 1 | 100.00 | |||
| spi_host_passthrough_mode | 1.000s | 121.535us | 1 | 1 | 100.00 | |
| cpol_cpha | 1 | 1 | 100.00 | |||
| spi_host_speed | 13.000s | 130.545us | 1 | 1 | 100.00 | |
| full_cycle | 1 | 1 | 100.00 | |||
| spi_host_speed | 13.000s | 130.545us | 1 | 1 | 100.00 | |
| duplex | 1 | 1 | 100.00 | |||
| spi_host_smoke | 34.000s | 3781.107us | 1 | 1 | 100.00 | |
| tx_rx_only | 1 | 1 | 100.00 | |||
| spi_host_smoke | 34.000s | 3781.107us | 1 | 1 | 100.00 | |
| stress_all | 1 | 1 | 100.00 | |||
| spi_host_stress_all | 2.000s | 83.505us | 1 | 1 | 100.00 | |
| spien | 1 | 1 | 100.00 | |||
| spi_host_spien | 4.000s | 925.148us | 1 | 1 | 100.00 | |
| stall | 1 | 1 | 100.00 | |||
| spi_host_status_stall | 63.000s | 8832.627us | 1 | 1 | 100.00 | |
| Idlecsbactive | 1 | 1 | 100.00 | |||
| spi_host_idlecsbactive | 2.000s | 37.792us | 1 | 1 | 100.00 | |
| data_fifo_status | 1 | 1 | 100.00 | |||
| spi_host_overflow_underflow | 2.000s | 176.403us | 1 | 1 | 100.00 | |
| alert_test | 1 | 1 | 100.00 | |||
| spi_host_alert_test | 2.000s | 16.669us | 1 | 1 | 100.00 | |
| intr_test | 1 | 1 | 100.00 | |||
| spi_host_intr_test | 2.000s | 17.967us | 1 | 1 | 100.00 | |
| tl_d_oob_addr_access | 1 | 1 | 100.00 | |||
| spi_host_tl_errors | 2.000s | 106.767us | 1 | 1 | 100.00 | |
| tl_d_illegal_access | 1 | 1 | 100.00 | |||
| spi_host_tl_errors | 2.000s | 106.767us | 1 | 1 | 100.00 | |
| tl_d_outstanding_access | 4 | 4 | 100.00 | |||
| spi_host_csr_hw_reset | 1.000s | 29.276us | 1 | 1 | 100.00 | |
| spi_host_csr_rw | 2.000s | 31.160us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 2.000s | 170.579us | 1 | 1 | 100.00 | |
| spi_host_same_csr_outstanding | 3.000s | 29.490us | 1 | 1 | 100.00 | |
| tl_d_partial_access | 4 | 4 | 100.00 | |||
| spi_host_csr_hw_reset | 1.000s | 29.276us | 1 | 1 | 100.00 | |
| spi_host_csr_rw | 2.000s | 31.160us | 1 | 1 | 100.00 | |
| spi_host_csr_aliasing | 2.000s | 170.579us | 1 | 1 | 100.00 | |
| spi_host_same_csr_outstanding | 3.000s | 29.490us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| tl_intg_err | 2 | 2 | 100.00 | |||
| spi_host_sec_cm | 2.000s | 297.102us | 1 | 1 | 100.00 | |
| spi_host_tl_intg_err | 2.000s | 141.865us | 1 | 1 | 100.00 | |
| sec_cm_bus_integrity | 1 | 1 | 100.00 | |||
| spi_host_tl_intg_err | 2.000s | 141.865us | 1 | 1 | 100.00 | |
| Testpoint | Test | Max Runtime | Sim Time | Pass | Total | % |
|---|---|---|---|---|---|---|
| Unmapped | 1 | 1 | 100.00 | |||
| spi_host_upper_range_clkdiv | 268.000s | 12771.876us | 1 | 1 | 100.00 | |