Simulation Results: sram_ctrl

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 96.01
  • line
  • 99.07
  • cond
  • 92.66
  • toggle
  • 90.66
  • fsm
  • 100.0
  • branch
  • 97.98
  • assert
  • 95.79
  • group
  • 95.92
Validation stages
V1
95.00%
V2
100.00%
V2S
72.92%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
sram_ctrl_smoke 5.000s 704.100us 2 2 100.00
csr_hw_reset 2 2 100.00
sram_ctrl_csr_hw_reset 0.710s 66.363us 2 2 100.00
csr_rw 2 2 100.00
sram_ctrl_csr_rw 0.760s 39.662us 2 2 100.00
csr_bit_bash 2 2 100.00
sram_ctrl_csr_bit_bash 1.260s 318.997us 2 2 100.00
csr_aliasing 2 2 100.00
sram_ctrl_csr_aliasing 0.890s 54.427us 2 2 100.00
csr_mem_rw_with_rand_reset 1 2 50.00
sram_ctrl_csr_mem_rw_with_rand_reset 2.720s 2595.590us 1 2 50.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
sram_ctrl_csr_rw 0.760s 39.662us 2 2 100.00
sram_ctrl_csr_aliasing 0.890s 54.427us 2 2 100.00
mem_walk 2 2 100.00
sram_ctrl_mem_walk 244.630s 23256.700us 2 2 100.00
mem_partial_access 2 2 100.00
sram_ctrl_mem_partial_access 105.000s 4767.331us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
multiple_keys 2 2 100.00
sram_ctrl_multiple_keys 705.500s 19699.411us 2 2 100.00
stress_pipeline 2 2 100.00
sram_ctrl_stress_pipeline 216.200s 4578.334us 2 2 100.00
bijection 2 2 100.00
sram_ctrl_bijection 550.280s 190189.550us 2 2 100.00
access_during_key_req 2 2 100.00
sram_ctrl_access_during_key_req 991.250s 19607.218us 2 2 100.00
lc_escalation 2 2 100.00
sram_ctrl_lc_escalation 49.540s 16067.586us 2 2 100.00
executable 2 2 100.00
sram_ctrl_executable 486.950s 26627.548us 2 2 100.00
partial_access 4 4 100.00
sram_ctrl_partial_access 42.020s 2475.614us 2 2 100.00
sram_ctrl_partial_access_b2b 291.070s 17798.652us 2 2 100.00
max_throughput 6 6 100.00
sram_ctrl_max_throughput 50.250s 796.263us 2 2 100.00
sram_ctrl_throughput_w_partial_write 14.600s 2511.114us 2 2 100.00
sram_ctrl_throughput_w_readback 55.480s 930.377us 2 2 100.00
regwen 2 2 100.00
sram_ctrl_regwen 703.640s 7008.748us 2 2 100.00
ram_cfg 2 2 100.00
sram_ctrl_ram_cfg 2.700s 611.424us 2 2 100.00
stress_all 2 2 100.00
sram_ctrl_stress_all 1659.830s 54117.634us 2 2 100.00
alert_test 2 2 100.00
sram_ctrl_alert_test 0.850s 82.025us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
sram_ctrl_tl_errors 2.970s 546.713us 2 2 100.00
tl_d_illegal_access 2 2 100.00
sram_ctrl_tl_errors 2.970s 546.713us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.710s 66.363us 2 2 100.00
sram_ctrl_csr_rw 0.760s 39.662us 2 2 100.00
sram_ctrl_csr_aliasing 0.890s 54.427us 2 2 100.00
sram_ctrl_same_csr_outstanding 0.780s 22.663us 2 2 100.00
tl_d_partial_access 8 8 100.00
sram_ctrl_csr_hw_reset 0.710s 66.363us 2 2 100.00
sram_ctrl_csr_rw 0.760s 39.662us 2 2 100.00
sram_ctrl_csr_aliasing 0.890s 54.427us 2 2 100.00
sram_ctrl_same_csr_outstanding 0.780s 22.663us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
passthru_mem_tl_intg_err 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.120s 46215.216us 2 2 100.00
tl_intg_err 2 4 50.00
sram_ctrl_tl_intg_err 1.250s 610.543us 2 2 100.00
sram_ctrl_sec_cm 0.830s 5.497us 0 2 0.00
prim_count_check 0 2 0.00
sram_ctrl_sec_cm 0.830s 5.497us 0 2 0.00
sec_cm_bus_integrity 2 2 100.00
sram_ctrl_tl_intg_err 1.250s 610.543us 2 2 100.00
sec_cm_ctrl_config_regwen 2 2 100.00
sram_ctrl_regwen 703.640s 7008.748us 2 2 100.00
sec_cm_readback_config_regwen 2 2 100.00
sram_ctrl_regwen 703.640s 7008.748us 2 2 100.00
sec_cm_exec_config_regwen 2 2 100.00
sram_ctrl_csr_rw 0.760s 39.662us 2 2 100.00
sec_cm_exec_config_mubi 2 2 100.00
sram_ctrl_executable 486.950s 26627.548us 2 2 100.00
sec_cm_exec_intersig_mubi 2 2 100.00
sram_ctrl_executable 486.950s 26627.548us 2 2 100.00
sec_cm_lc_hw_debug_en_intersig_mubi 2 2 100.00
sram_ctrl_executable 486.950s 26627.548us 2 2 100.00
sec_cm_lc_escalate_en_intersig_mubi 2 2 100.00
sram_ctrl_lc_escalation 49.540s 16067.586us 2 2 100.00
sec_cm_prim_ram_ctrl_mubi 2 2 100.00
sram_ctrl_mubi_enc_err 4.530s 705.735us 2 2 100.00
sec_cm_mem_integrity 2 2 100.00
sram_ctrl_passthru_mem_tl_intg_err 18.120s 46215.216us 2 2 100.00
sec_cm_mem_readback 1 2 50.00
sram_ctrl_readback_err 3.650s 693.231us 1 2 50.00
sec_cm_mem_scramble 2 2 100.00
sram_ctrl_smoke 5.000s 704.100us 2 2 100.00
sec_cm_addr_scramble 2 2 100.00
sram_ctrl_smoke 5.000s 704.100us 2 2 100.00
sec_cm_instr_bus_lc_gated 2 2 100.00
sram_ctrl_executable 486.950s 26627.548us 2 2 100.00
sec_cm_ram_tl_lc_gate_fsm_sparse 0 2 0.00
sram_ctrl_sec_cm 0.830s 5.497us 0 2 0.00
sec_cm_key_global_esc 2 2 100.00
sram_ctrl_lc_escalation 49.540s 16067.586us 2 2 100.00
sec_cm_key_local_esc 0 2 0.00
sram_ctrl_sec_cm 0.830s 5.497us 0 2 0.00
sec_cm_init_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.830s 5.497us 0 2 0.00
sec_cm_scramble_key_sideload 2 2 100.00
sram_ctrl_smoke 5.000s 704.100us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 0 2 0.00
sram_ctrl_sec_cm 0.830s 5.497us 0 2 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
sram_ctrl_stress_all_with_rand_reset 69.140s 1797.991us 2 2 100.00