Simulation Results: sysrst_ctrl

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.65
  • line
  • 97.1
  • cond
  • 94.74
  • toggle
  • 100.0
  • fsm
  • 75.0
  • branch
  • 97.26
  • assert
  • 92.62
  • group
  • 70.85
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
sysrst_ctrl_smoke 4.440s 2108.471us 1 1 100.00
input_output_inverted 1 1 100.00
sysrst_ctrl_in_out_inverted 2.620s 2473.078us 1 1 100.00
combo_detect_ec_rst 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst 1.880s 2165.801us 1 1 100.00
combo_detect_ec_rst_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_ec_rst_with_pre_cond 5.190s 2507.361us 1 1 100.00
csr_hw_reset 1 1 100.00
sysrst_ctrl_csr_hw_reset 2.600s 4043.978us 1 1 100.00
csr_rw 1 1 100.00
sysrst_ctrl_csr_rw 1.690s 2178.345us 1 1 100.00
csr_bit_bash 1 1 100.00
sysrst_ctrl_csr_bit_bash 38.800s 39054.139us 1 1 100.00
csr_aliasing 1 1 100.00
sysrst_ctrl_csr_aliasing 9.070s 2583.431us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
sysrst_ctrl_csr_mem_rw_with_rand_reset 2.470s 2196.897us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
sysrst_ctrl_csr_rw 1.690s 2178.345us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.070s 2583.431us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
combo_detect 1 1 100.00
sysrst_ctrl_combo_detect 284.920s 152469.837us 1 1 100.00
combo_detect_with_pre_cond 1 1 100.00
sysrst_ctrl_combo_detect_with_pre_cond 95.900s 193771.147us 1 1 100.00
auto_block_key_outputs 1 1 100.00
sysrst_ctrl_auto_blk_key_output 7.720s 3374.526us 1 1 100.00
keyboard_input_triggered_interrupt 1 1 100.00
sysrst_ctrl_edge_detect 3.010s 2935.657us 1 1 100.00
pin_output_keyboard_inversion_control 1 1 100.00
sysrst_ctrl_pin_override_test 5.810s 2508.194us 1 1 100.00
pin_input_value_accessibility 1 1 100.00
sysrst_ctrl_pin_access_test 1.870s 2071.407us 1 1 100.00
ec_power_on_reset 1 1 100.00
sysrst_ctrl_ec_pwr_on_rst 3.550s 3049.994us 1 1 100.00
flash_write_protect_output 1 1 100.00
sysrst_ctrl_flash_wr_prot_out 5.440s 2613.716us 1 1 100.00
ultra_low_power_test 1 1 100.00
sysrst_ctrl_ultra_low_pwr 2.320s 5724.540us 1 1 100.00
sysrst_ctrl_feature_disable 1 1 100.00
sysrst_ctrl_feature_disable 66.310s 34490.029us 1 1 100.00
stress_all 1 1 100.00
sysrst_ctrl_stress_all 48.490s 50586.485us 1 1 100.00
alert_test 1 1 100.00
sysrst_ctrl_alert_test 4.340s 2011.240us 1 1 100.00
intr_test 1 1 100.00
sysrst_ctrl_intr_test 5.630s 2013.405us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
sysrst_ctrl_tl_errors 3.810s 2163.408us 1 1 100.00
tl_d_illegal_access 1 1 100.00
sysrst_ctrl_tl_errors 3.810s 2163.408us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.600s 4043.978us 1 1 100.00
sysrst_ctrl_csr_rw 1.690s 2178.345us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.070s 2583.431us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 18.890s 10144.667us 1 1 100.00
tl_d_partial_access 4 4 100.00
sysrst_ctrl_csr_hw_reset 2.600s 4043.978us 1 1 100.00
sysrst_ctrl_csr_rw 1.690s 2178.345us 1 1 100.00
sysrst_ctrl_csr_aliasing 9.070s 2583.431us 1 1 100.00
sysrst_ctrl_same_csr_outstanding 18.890s 10144.667us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
sysrst_ctrl_sec_cm 71.890s 42012.156us 1 1 100.00
sysrst_ctrl_tl_intg_err 13.070s 42724.240us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
sysrst_ctrl_tl_intg_err 13.070s 42724.240us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
sysrst_ctrl_stress_all_with_rand_reset 12.870s 23543.608us 1 1 100.00