Simulation Results: uart

 
19/11/2025 18:29:58 sha: 395232b json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 90.55
  • line
  • 99.17
  • cond
  • 96.85
  • toggle
  • 91.55
  • fsm
  • None
  • branch
  • 97.2
  • assert
  • 97.12
  • group
  • 61.42
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
uart_smoke 1.500s 532.502us 1 1 100.00
csr_hw_reset 1 1 100.00
uart_csr_hw_reset 0.630s 15.492us 1 1 100.00
csr_rw 1 1 100.00
uart_csr_rw 0.570s 40.777us 1 1 100.00
csr_bit_bash 1 1 100.00
uart_csr_bit_bash 1.870s 298.261us 1 1 100.00
csr_aliasing 1 1 100.00
uart_csr_aliasing 0.630s 45.639us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
uart_csr_mem_rw_with_rand_reset 0.990s 26.581us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
uart_csr_rw 0.570s 40.777us 1 1 100.00
uart_csr_aliasing 0.630s 45.639us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
base_random_seq 1 1 100.00
uart_tx_rx 31.030s 302659.313us 1 1 100.00
parity 2 2 100.00
uart_smoke 1.500s 532.502us 1 1 100.00
uart_tx_rx 31.030s 302659.313us 1 1 100.00
parity_error 2 2 100.00
uart_intr 746.920s 602854.955us 1 1 100.00
uart_rx_parity_err 60.630s 63018.739us 1 1 100.00
watermark 2 2 100.00
uart_tx_rx 31.030s 302659.313us 1 1 100.00
uart_intr 746.920s 602854.955us 1 1 100.00
fifo_full 1 1 100.00
uart_fifo_full 31.810s 30638.014us 1 1 100.00
fifo_overflow 1 1 100.00
uart_fifo_overflow 55.750s 183755.631us 1 1 100.00
fifo_reset 1 1 100.00
uart_fifo_reset 44.950s 164078.588us 1 1 100.00
rx_frame_err 1 1 100.00
uart_intr 746.920s 602854.955us 1 1 100.00
rx_break_err 1 1 100.00
uart_intr 746.920s 602854.955us 1 1 100.00
rx_timeout 1 1 100.00
uart_intr 746.920s 602854.955us 1 1 100.00
perf 1 1 100.00
uart_perf 895.500s 22066.275us 1 1 100.00
sys_loopback 1 1 100.00
uart_loopback 1.800s 1018.726us 1 1 100.00
line_loopback 1 1 100.00
uart_loopback 1.800s 1018.726us 1 1 100.00
rx_noise_filter 1 1 100.00
uart_noise_filter 10.700s 9036.141us 1 1 100.00
rx_start_bit_filter 1 1 100.00
uart_rx_start_bit_filter 3.120s 34460.258us 1 1 100.00
tx_overide 1 1 100.00
uart_tx_ovrd 1.190s 1003.429us 1 1 100.00
rx_oversample 1 1 100.00
uart_rx_oversample 13.850s 4920.954us 1 1 100.00
long_b2b_transfer 1 1 100.00
uart_long_xfer_wo_dly 85.340s 145980.573us 1 1 100.00
stress_all 1 1 100.00
uart_stress_all 423.070s 425792.440us 1 1 100.00
alert_test 1 1 100.00
uart_alert_test 0.610s 68.871us 1 1 100.00
intr_test 1 1 100.00
uart_intr_test 0.560s 33.870us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
uart_tl_errors 1.030s 44.641us 1 1 100.00
tl_d_illegal_access 1 1 100.00
uart_tl_errors 1.030s 44.641us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
uart_csr_hw_reset 0.630s 15.492us 1 1 100.00
uart_csr_rw 0.570s 40.777us 1 1 100.00
uart_csr_aliasing 0.630s 45.639us 1 1 100.00
uart_same_csr_outstanding 0.720s 210.590us 1 1 100.00
tl_d_partial_access 4 4 100.00
uart_csr_hw_reset 0.630s 15.492us 1 1 100.00
uart_csr_rw 0.570s 40.777us 1 1 100.00
uart_csr_aliasing 0.630s 45.639us 1 1 100.00
uart_same_csr_outstanding 0.720s 210.590us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
uart_sec_cm 0.880s 127.697us 1 1 100.00
uart_tl_intg_err 0.800s 231.260us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
uart_tl_intg_err 0.800s 231.260us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
uart_stress_all_with_rand_reset 19.240s 7587.753us 1 1 100.00