Simulation Results: adc_ctrl

 
20/11/2025 19:30:26 sha: 1f7db17 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 88.17
  • line
  • 99.05
  • cond
  • 95.53
  • toggle
  • 100.0
  • fsm
  • 86.49
  • branch
  • 98.64
  • assert
  • 95.79
  • group
  • 41.69
Validation stages
V1
100.00%
V2
95.83%
V2S
100.00%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
adc_ctrl_smoke 5.640s 6022.647us 1 1 100.00
csr_hw_reset 1 1 100.00
adc_ctrl_csr_hw_reset 1.350s 1210.068us 1 1 100.00
csr_rw 1 1 100.00
adc_ctrl_csr_rw 1.610s 496.870us 1 1 100.00
csr_bit_bash 1 1 100.00
adc_ctrl_csr_bit_bash 14.740s 26721.698us 1 1 100.00
csr_aliasing 1 1 100.00
adc_ctrl_csr_aliasing 1.520s 1128.745us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
adc_ctrl_csr_mem_rw_with_rand_reset 1.200s 948.194us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
adc_ctrl_csr_rw 1.610s 496.870us 1 1 100.00
adc_ctrl_csr_aliasing 1.520s 1128.745us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
filters_polled 1 1 100.00
adc_ctrl_filters_polled 592.600s 327871.051us 1 1 100.00
filters_polled_fixed 1 1 100.00
adc_ctrl_filters_polled_fixed 124.470s 320745.003us 1 1 100.00
filters_interrupt 1 1 100.00
adc_ctrl_filters_interrupt 65.760s 161874.021us 1 1 100.00
filters_interrupt_fixed 1 1 100.00
adc_ctrl_filters_interrupt_fixed 148.280s 163394.247us 1 1 100.00
filters_wakeup 1 1 100.00
adc_ctrl_filters_wakeup 112.870s 197654.260us 1 1 100.00
filters_wakeup_fixed 1 1 100.00
adc_ctrl_filters_wakeup_fixed 391.820s 201003.725us 1 1 100.00
filters_both 1 1 100.00
adc_ctrl_filters_both 147.590s 333666.931us 1 1 100.00
clock_gating 0 1 0.00
adc_ctrl_clock_gating 4.280s 13584.429us 0 1 0.00
poweron_counter 1 1 100.00
adc_ctrl_poweron_counter 5.650s 4651.500us 1 1 100.00
lowpower_counter 1 1 100.00
adc_ctrl_lowpower_counter 64.770s 43268.529us 1 1 100.00
fsm_reset 1 1 100.00
adc_ctrl_fsm_reset 12.860s 82396.790us 1 1 100.00
stress_all 1 1 100.00
adc_ctrl_stress_all 179.950s 524973.409us 1 1 100.00
alert_test 1 1 100.00
adc_ctrl_alert_test 1.180s 292.783us 1 1 100.00
intr_test 1 1 100.00
adc_ctrl_intr_test 1.070s 508.345us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
adc_ctrl_tl_errors 2.810s 601.722us 1 1 100.00
tl_d_illegal_access 1 1 100.00
adc_ctrl_tl_errors 2.810s 601.722us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.350s 1210.068us 1 1 100.00
adc_ctrl_csr_rw 1.610s 496.870us 1 1 100.00
adc_ctrl_csr_aliasing 1.520s 1128.745us 1 1 100.00
adc_ctrl_same_csr_outstanding 8.010s 4728.996us 1 1 100.00
tl_d_partial_access 4 4 100.00
adc_ctrl_csr_hw_reset 1.350s 1210.068us 1 1 100.00
adc_ctrl_csr_rw 1.610s 496.870us 1 1 100.00
adc_ctrl_csr_aliasing 1.520s 1128.745us 1 1 100.00
adc_ctrl_same_csr_outstanding 8.010s 4728.996us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
adc_ctrl_tl_intg_err 9.860s 4944.735us 1 1 100.00
adc_ctrl_sec_cm 1.450s 4508.440us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
adc_ctrl_tl_intg_err 9.860s 4944.735us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 1 1 100.00
adc_ctrl_stress_all_with_rand_reset 7.680s 2738.801us 1 1 100.00