Simulation Results: edn

 
20/11/2025 19:30:26 sha: 1f7db17 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 79.46
  • line
  • 97.06
  • cond
  • 82.93
  • toggle
  • 72.45
  • fsm
  • 46.51
  • branch
  • 89.44
  • assert
  • 93.78
  • group
  • 74.05
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
edn_smoke 1.170s 27.577us 1 1 100.00
csr_hw_reset 1 1 100.00
edn_csr_hw_reset 1.010s 85.495us 1 1 100.00
csr_rw 1 1 100.00
edn_csr_rw 0.980s 74.329us 1 1 100.00
csr_bit_bash 1 1 100.00
edn_csr_bit_bash 3.620s 696.525us 1 1 100.00
csr_aliasing 1 1 100.00
edn_csr_aliasing 0.860s 26.945us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
edn_csr_mem_rw_with_rand_reset 1.360s 23.276us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
edn_csr_rw 0.980s 74.329us 1 1 100.00
edn_csr_aliasing 0.860s 26.945us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
firmware 1 1 100.00
edn_genbits 1.240s 55.507us 1 1 100.00
csrng_commands 1 1 100.00
edn_genbits 1.240s 55.507us 1 1 100.00
genbits 1 1 100.00
edn_genbits 1.240s 55.507us 1 1 100.00
interrupts 1 1 100.00
edn_intr 1.070s 26.582us 1 1 100.00
alerts 1 1 100.00
edn_alert 1.100s 92.892us 1 1 100.00
errs 1 1 100.00
edn_err 1.130s 26.701us 1 1 100.00
disable 2 2 100.00
edn_disable 0.930s 36.616us 1 1 100.00
edn_disable_auto_req_mode 1.410s 52.317us 1 1 100.00
stress_all 1 1 100.00
edn_stress_all 3.250s 893.180us 1 1 100.00
intr_test 1 1 100.00
edn_intr_test 0.830s 14.723us 1 1 100.00
alert_test 1 1 100.00
edn_alert_test 1.010s 50.497us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
edn_tl_errors 1.800s 96.372us 1 1 100.00
tl_d_illegal_access 1 1 100.00
edn_tl_errors 1.800s 96.372us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
edn_csr_hw_reset 1.010s 85.495us 1 1 100.00
edn_csr_rw 0.980s 74.329us 1 1 100.00
edn_csr_aliasing 0.860s 26.945us 1 1 100.00
edn_same_csr_outstanding 0.970s 63.348us 1 1 100.00
tl_d_partial_access 4 4 100.00
edn_csr_hw_reset 1.010s 85.495us 1 1 100.00
edn_csr_rw 0.980s 74.329us 1 1 100.00
edn_csr_aliasing 0.860s 26.945us 1 1 100.00
edn_same_csr_outstanding 0.970s 63.348us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
edn_tl_intg_err 1.590s 54.784us 1 1 100.00
edn_sec_cm 4.200s 676.482us 1 1 100.00
sec_cm_config_regwen 1 1 100.00
edn_regwen 1.180s 79.228us 1 1 100.00
sec_cm_config_mubi 1 1 100.00
edn_alert 1.100s 92.892us 1 1 100.00
sec_cm_main_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.200s 676.482us 1 1 100.00
sec_cm_ack_sm_fsm_sparse 1 1 100.00
edn_sec_cm 4.200s 676.482us 1 1 100.00
sec_cm_fifo_ctr_redun 1 1 100.00
edn_sec_cm 4.200s 676.482us 1 1 100.00
sec_cm_ctr_redun 1 1 100.00
edn_sec_cm 4.200s 676.482us 1 1 100.00
sec_cm_main_sm_ctr_local_esc 2 2 100.00
edn_alert 1.100s 92.892us 1 1 100.00
edn_sec_cm 4.200s 676.482us 1 1 100.00
sec_cm_cs_rdata_bus_consistency 1 1 100.00
edn_alert 1.100s 92.892us 1 1 100.00
sec_cm_tile_link_bus_integrity 1 1 100.00
edn_tl_intg_err 1.590s 54.784us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
edn_stress_all_with_rand_reset 0.000s 0.000us 0 1 0.00