Simulation Results: hmac

 
20/11/2025 19:30:26 sha: 1f7db17 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 89.07
  • line
  • 99.16
  • cond
  • 95.67
  • toggle
  • 100.0
  • fsm
  • 91.18
  • branch
  • 98.18
  • assert
  • 96.42
  • group
  • 42.89
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
100.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
hmac_smoke 6.610s 2011.023us 1 1 100.00
csr_hw_reset 1 1 100.00
hmac_csr_hw_reset 0.790s 29.696us 1 1 100.00
csr_rw 1 1 100.00
hmac_csr_rw 0.850s 17.739us 1 1 100.00
csr_bit_bash 1 1 100.00
hmac_csr_bit_bash 7.190s 216.064us 1 1 100.00
csr_aliasing 1 1 100.00
hmac_csr_aliasing 2.310s 112.157us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
hmac_csr_mem_rw_with_rand_reset 1.010s 38.100us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
hmac_csr_rw 0.850s 17.739us 1 1 100.00
hmac_csr_aliasing 2.310s 112.157us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
long_msg 1 1 100.00
hmac_long_msg 54.940s 1164.480us 1 1 100.00
back_pressure 1 1 100.00
hmac_back_pressure 6.310s 622.746us 1 1 100.00
test_vectors 6 6 100.00
hmac_test_sha256_vectors 13.250s 179.170us 1 1 100.00
hmac_test_sha384_vectors 23.110s 733.594us 1 1 100.00
hmac_test_sha512_vectors 23.850s 871.720us 1 1 100.00
hmac_test_hmac256_vectors 8.590s 1053.328us 1 1 100.00
hmac_test_hmac384_vectors 11.170s 343.777us 1 1 100.00
hmac_test_hmac512_vectors 8.930s 511.355us 1 1 100.00
burst_wr 1 1 100.00
hmac_burst_wr 6.250s 601.838us 1 1 100.00
datapath_stress 1 1 100.00
hmac_datapath_stress 934.500s 6487.300us 1 1 100.00
error 1 1 100.00
hmac_error 43.150s 4742.120us 1 1 100.00
wipe_secret 1 1 100.00
hmac_wipe_secret 117.690s 33039.607us 1 1 100.00
save_and_restore 6 6 100.00
hmac_smoke 6.610s 2011.023us 1 1 100.00
hmac_long_msg 54.940s 1164.480us 1 1 100.00
hmac_back_pressure 6.310s 622.746us 1 1 100.00
hmac_datapath_stress 934.500s 6487.300us 1 1 100.00
hmac_burst_wr 6.250s 601.838us 1 1 100.00
hmac_stress_all 1413.920s 38622.350us 1 1 100.00
fifo_empty_status_interrupt 11 11 100.00
hmac_smoke 6.610s 2011.023us 1 1 100.00
hmac_long_msg 54.940s 1164.480us 1 1 100.00
hmac_back_pressure 6.310s 622.746us 1 1 100.00
hmac_datapath_stress 934.500s 6487.300us 1 1 100.00
hmac_wipe_secret 117.690s 33039.607us 1 1 100.00
hmac_test_sha256_vectors 13.250s 179.170us 1 1 100.00
hmac_test_sha384_vectors 23.110s 733.594us 1 1 100.00
hmac_test_sha512_vectors 23.850s 871.720us 1 1 100.00
hmac_test_hmac256_vectors 8.590s 1053.328us 1 1 100.00
hmac_test_hmac384_vectors 11.170s 343.777us 1 1 100.00
hmac_test_hmac512_vectors 8.930s 511.355us 1 1 100.00
wide_digest_configurable_key_length 14 14 100.00
hmac_smoke 6.610s 2011.023us 1 1 100.00
hmac_long_msg 54.940s 1164.480us 1 1 100.00
hmac_back_pressure 6.310s 622.746us 1 1 100.00
hmac_datapath_stress 934.500s 6487.300us 1 1 100.00
hmac_burst_wr 6.250s 601.838us 1 1 100.00
hmac_error 43.150s 4742.120us 1 1 100.00
hmac_wipe_secret 117.690s 33039.607us 1 1 100.00
hmac_test_sha256_vectors 13.250s 179.170us 1 1 100.00
hmac_test_sha384_vectors 23.110s 733.594us 1 1 100.00
hmac_test_sha512_vectors 23.850s 871.720us 1 1 100.00
hmac_test_hmac256_vectors 8.590s 1053.328us 1 1 100.00
hmac_test_hmac384_vectors 11.170s 343.777us 1 1 100.00
hmac_test_hmac512_vectors 8.930s 511.355us 1 1 100.00
hmac_stress_all 1413.920s 38622.350us 1 1 100.00
stress_all 1 1 100.00
hmac_stress_all 1413.920s 38622.350us 1 1 100.00
alert_test 1 1 100.00
hmac_alert_test 0.800s 54.983us 1 1 100.00
intr_test 1 1 100.00
hmac_intr_test 0.630s 11.923us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
hmac_tl_errors 2.520s 186.424us 1 1 100.00
tl_d_illegal_access 1 1 100.00
hmac_tl_errors 2.520s 186.424us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
hmac_csr_hw_reset 0.790s 29.696us 1 1 100.00
hmac_csr_rw 0.850s 17.739us 1 1 100.00
hmac_csr_aliasing 2.310s 112.157us 1 1 100.00
hmac_same_csr_outstanding 1.090s 88.320us 1 1 100.00
tl_d_partial_access 4 4 100.00
hmac_csr_hw_reset 0.790s 29.696us 1 1 100.00
hmac_csr_rw 0.850s 17.739us 1 1 100.00
hmac_csr_aliasing 2.310s 112.157us 1 1 100.00
hmac_same_csr_outstanding 1.090s 88.320us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
hmac_tl_intg_err 1.550s 338.591us 1 1 100.00
hmac_sec_cm 1.260s 63.596us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
hmac_tl_intg_err 1.550s 338.591us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
write_config_and_secret_key_during_msg_wr 1 1 100.00
hmac_smoke 6.610s 2011.023us 1 1 100.00
stress_reset 1 1 100.00
hmac_stress_reset 3.550s 1118.089us 1 1 100.00
stress_all_with_rand_reset 1 1 100.00
hmac_stress_all_with_rand_reset 179.870s 3706.215us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
hmac_directed 2.630s 787.903us 1 1 100.00