| host_error_intr |
0 |
1 |
0.00 |
|
i2c_host_error_intr |
2.150s |
69.185us |
0 |
1 |
0.00
|
| host_stress_all |
0 |
1 |
0.00 |
|
i2c_host_stress_all |
77.860s |
3621.375us |
0 |
1 |
0.00
|
| host_maxperf |
1 |
1 |
100.00 |
|
i2c_host_perf |
235.240s |
70509.981us |
1 |
1 |
100.00
|
| host_override |
1 |
1 |
100.00 |
|
i2c_host_override |
0.780s |
22.579us |
1 |
1 |
100.00
|
| host_fifo_watermark |
1 |
1 |
100.00 |
|
i2c_host_fifo_watermark |
154.620s |
3677.261us |
1 |
1 |
100.00
|
| host_fifo_overflow |
1 |
1 |
100.00 |
|
i2c_host_fifo_overflow |
81.430s |
10317.922us |
1 |
1 |
100.00
|
| host_fifo_reset |
3 |
3 |
100.00 |
|
i2c_host_fifo_reset_fmt |
1.040s |
153.803us |
1 |
1 |
100.00
|
|
i2c_host_fifo_fmt_empty |
4.490s |
4533.777us |
1 |
1 |
100.00
|
|
i2c_host_fifo_reset_rx |
3.970s |
819.457us |
1 |
1 |
100.00
|
| host_fifo_full |
1 |
1 |
100.00 |
|
i2c_host_fifo_full |
54.820s |
16279.026us |
1 |
1 |
100.00
|
| host_timeout |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
5.850s |
532.901us |
1 |
1 |
100.00
|
| i2c_host_mode_toggle |
0 |
1 |
0.00 |
|
i2c_host_mode_toggle |
1.020s |
26.514us |
0 |
1 |
0.00
|
| target_glitch |
0 |
1 |
0.00 |
|
i2c_target_glitch |
3.160s |
468.435us |
0 |
1 |
0.00
|
| target_stress_all |
1 |
1 |
100.00 |
|
i2c_target_stress_all |
95.050s |
27600.820us |
1 |
1 |
100.00
|
| target_maxperf |
1 |
1 |
100.00 |
|
i2c_target_perf |
4.340s |
657.251us |
1 |
1 |
100.00
|
| target_fifo_empty |
2 |
2 |
100.00 |
|
i2c_target_stress_rd |
45.460s |
8060.978us |
1 |
1 |
100.00
|
|
i2c_target_intr_smoke |
4.000s |
1008.803us |
1 |
1 |
100.00
|
| target_fifo_reset |
2 |
2 |
100.00 |
|
i2c_target_fifo_reset_acq |
1.040s |
167.208us |
1 |
1 |
100.00
|
|
i2c_target_fifo_reset_tx |
1.260s |
271.858us |
1 |
1 |
100.00
|
| target_fifo_full |
3 |
3 |
100.00 |
|
i2c_target_stress_wr |
802.690s |
61511.710us |
1 |
1 |
100.00
|
|
i2c_target_stress_rd |
45.460s |
8060.978us |
1 |
1 |
100.00
|
|
i2c_target_intr_stress_wr |
51.400s |
7448.967us |
1 |
1 |
100.00
|
| target_timeout |
1 |
1 |
100.00 |
|
i2c_target_timeout |
6.460s |
4579.785us |
1 |
1 |
100.00
|
| target_clock_stretch |
1 |
1 |
100.00 |
|
i2c_target_stretch |
12.180s |
1787.886us |
1 |
1 |
100.00
|
| bad_address |
1 |
1 |
100.00 |
|
i2c_target_bad_addr |
3.910s |
906.510us |
1 |
1 |
100.00
|
| target_mode_glitch |
0 |
1 |
0.00 |
|
i2c_target_hrst |
22.480s |
10013.168us |
0 |
1 |
0.00
|
| target_fifo_watermark |
2 |
2 |
100.00 |
|
i2c_target_fifo_watermarks_acq |
3.910s |
2021.301us |
1 |
1 |
100.00
|
|
i2c_target_fifo_watermarks_tx |
1.730s |
589.498us |
1 |
1 |
100.00
|
| host_mode_config_perf |
2 |
2 |
100.00 |
|
i2c_host_perf |
235.240s |
70509.981us |
1 |
1 |
100.00
|
|
i2c_host_perf_precise |
8.940s |
228.094us |
1 |
1 |
100.00
|
| host_mode_clock_stretching |
1 |
1 |
100.00 |
|
i2c_host_stretch_timeout |
5.850s |
532.901us |
1 |
1 |
100.00
|
| target_mode_tx_stretch_ctrl |
1 |
1 |
100.00 |
|
i2c_target_tx_stretch_ctrl |
4.710s |
252.824us |
1 |
1 |
100.00
|
| target_mode_nack_generation |
2 |
3 |
66.67 |
|
i2c_target_nack_acqfull |
2.370s |
2168.747us |
1 |
1 |
100.00
|
|
i2c_target_nack_acqfull_addr |
4.020s |
513.145us |
1 |
1 |
100.00
|
|
i2c_target_nack_txstretch |
2.040s |
163.056us |
0 |
1 |
0.00
|
| host_mode_halt_on_nak |
1 |
1 |
100.00 |
|
i2c_host_may_nack |
29.860s |
6503.771us |
1 |
1 |
100.00
|
| target_mode_smbus_maxlen |
1 |
1 |
100.00 |
|
i2c_target_smbus_maxlen |
1.760s |
476.608us |
1 |
1 |
100.00
|
| alert_test |
1 |
1 |
100.00 |
|
i2c_alert_test |
0.850s |
41.585us |
1 |
1 |
100.00
|
| intr_test |
1 |
1 |
100.00 |
|
i2c_intr_test |
0.740s |
25.160us |
1 |
1 |
100.00
|
| tl_d_oob_addr_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
2.100s |
48.413us |
1 |
1 |
100.00
|
| tl_d_illegal_access |
1 |
1 |
100.00 |
|
i2c_tl_errors |
2.100s |
48.413us |
1 |
1 |
100.00
|
| tl_d_outstanding_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.990s |
22.338us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.720s |
26.415us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.480s |
183.843us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
1.220s |
21.667us |
1 |
1 |
100.00
|
| tl_d_partial_access |
4 |
4 |
100.00 |
|
i2c_csr_hw_reset |
0.990s |
22.338us |
1 |
1 |
100.00
|
|
i2c_csr_rw |
0.720s |
26.415us |
1 |
1 |
100.00
|
|
i2c_csr_aliasing |
1.480s |
183.843us |
1 |
1 |
100.00
|
|
i2c_same_csr_outstanding |
1.220s |
21.667us |
1 |
1 |
100.00
|