Simulation Results: pattgen

 
20/11/2025 19:30:26 sha: 1f7db17 json Branch: master Tool: xcelium [unknown]
Coverage statistics
  • score
  • 98.39
  • block
  • 100.0
  • branch
  • 100.0
  • statement
  • 100.0
  • expression
  • 97.75
  • toggle
  • 96.61
  • fsm
  • None
  • assertion
  • 96.95
  • covergroup
  • 88.94
Validation stages
V1
100.00%
V2
100.00%
V2S
100.00%
V3
0.00%
unmapped
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pattgen_smoke 1.000s 118.244us 1 1 100.00
csr_hw_reset 1 1 100.00
pattgen_csr_hw_reset 1.000s 23.629us 1 1 100.00
csr_rw 1 1 100.00
pattgen_csr_rw 1.000s 16.945us 1 1 100.00
csr_bit_bash 1 1 100.00
pattgen_csr_bit_bash 3.000s 2292.036us 1 1 100.00
csr_aliasing 1 1 100.00
pattgen_csr_aliasing 1.000s 148.607us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pattgen_csr_mem_rw_with_rand_reset 2.000s 34.837us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pattgen_csr_rw 1.000s 16.945us 1 1 100.00
pattgen_csr_aliasing 1.000s 148.607us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
perf 1 1 100.00
pattgen_perf 96.000s 4112.466us 1 1 100.00
cnt_rollover 1 1 100.00
cnt_rollover 14.000s 2053.131us 1 1 100.00
error 1 1 100.00
pattgen_error 2.000s 17.515us 1 1 100.00
stress_all 1 1 100.00
pattgen_stress_all 2.000s 792.034us 1 1 100.00
alert_test 1 1 100.00
pattgen_alert_test 2.000s 32.839us 1 1 100.00
intr_test 1 1 100.00
pattgen_intr_test 1.000s 18.275us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pattgen_tl_errors 2.000s 88.932us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pattgen_tl_errors 2.000s 88.932us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 23.629us 1 1 100.00
pattgen_csr_rw 1.000s 16.945us 1 1 100.00
pattgen_csr_aliasing 1.000s 148.607us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 30.101us 1 1 100.00
tl_d_partial_access 4 4 100.00
pattgen_csr_hw_reset 1.000s 23.629us 1 1 100.00
pattgen_csr_rw 1.000s 16.945us 1 1 100.00
pattgen_csr_aliasing 1.000s 148.607us 1 1 100.00
pattgen_same_csr_outstanding 2.000s 30.101us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 2 2 100.00
pattgen_sec_cm 1.000s 244.170us 1 1 100.00
pattgen_tl_intg_err 2.000s 285.692us 1 1 100.00
sec_cm_bus_integrity 1 1 100.00
pattgen_tl_intg_err 2.000s 285.692us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 0 1 0.00
pattgen_stress_all_with_rand_reset 34.000s 14611.909us 0 1 0.00
Testpoint Test Max Runtime Sim Time Pass Total %
Unmapped 1 1 100.00
pattgen_inactive_level 2.000s 793.879us 1 1 100.00