Simulation Results: pwrmgr

 
20/11/2025 19:30:26 sha: 1f7db17 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 95.03
  • line
  • 98.92
  • cond
  • 93.92
  • toggle
  • 90.02
  • fsm
  • 94.0
  • branch
  • 95.42
  • assert
  • 96.08
  • group
  • 96.87
Validation stages
V1
100.00%
V2
100.00%
V2S
52.94%
V3
50.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 1 1 100.00
pwrmgr_smoke 0.680s 36.754us 1 1 100.00
csr_hw_reset 1 1 100.00
pwrmgr_csr_hw_reset 0.630s 24.751us 1 1 100.00
csr_rw 1 1 100.00
pwrmgr_csr_rw 0.600s 42.322us 1 1 100.00
csr_bit_bash 1 1 100.00
pwrmgr_csr_bit_bash 1.260s 157.405us 1 1 100.00
csr_aliasing 1 1 100.00
pwrmgr_csr_aliasing 0.790s 27.586us 1 1 100.00
csr_mem_rw_with_rand_reset 1 1 100.00
pwrmgr_csr_mem_rw_with_rand_reset 0.750s 135.148us 1 1 100.00
regwen_csr_and_corresponding_lockable_csr 2 2 100.00
pwrmgr_csr_rw 0.600s 42.322us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 27.586us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
wakeup 1 1 100.00
pwrmgr_wakeup 0.720s 170.234us 1 1 100.00
control_clks 1 1 100.00
pwrmgr_wakeup 0.720s 170.234us 1 1 100.00
aborted_low_power 2 2 100.00
pwrmgr_aborted_low_power 0.700s 116.209us 1 1 100.00
pwrmgr_lowpower_invalid 0.660s 89.898us 1 1 100.00
reset 2 2 100.00
pwrmgr_reset 0.670s 25.088us 1 1 100.00
pwrmgr_reset_invalid 0.770s 156.511us 1 1 100.00
main_power_glitch_reset 1 1 100.00
pwrmgr_reset 0.670s 25.088us 1 1 100.00
reset_wakeup_race 1 1 100.00
pwrmgr_wakeup_reset 0.690s 155.198us 1 1 100.00
lowpower_wakeup_race 1 1 100.00
pwrmgr_lowpower_wakeup_race 0.680s 117.411us 1 1 100.00
disable_rom_integrity_check 1 1 100.00
pwrmgr_disable_rom_integrity_check 1.090s 148.895us 1 1 100.00
stress_all 1 1 100.00
pwrmgr_stress_all 3.520s 1417.224us 1 1 100.00
intr_test 1 1 100.00
pwrmgr_intr_test 0.610s 19.926us 1 1 100.00
tl_d_oob_addr_access 1 1 100.00
pwrmgr_tl_errors 1.150s 286.447us 1 1 100.00
tl_d_illegal_access 1 1 100.00
pwrmgr_tl_errors 1.150s 286.447us 1 1 100.00
tl_d_outstanding_access 4 4 100.00
pwrmgr_csr_hw_reset 0.630s 24.751us 1 1 100.00
pwrmgr_csr_rw 0.600s 42.322us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 27.586us 1 1 100.00
pwrmgr_same_csr_outstanding 0.740s 70.687us 1 1 100.00
tl_d_partial_access 4 4 100.00
pwrmgr_csr_hw_reset 0.630s 24.751us 1 1 100.00
pwrmgr_csr_rw 0.600s 42.322us 1 1 100.00
pwrmgr_csr_aliasing 0.790s 27.586us 1 1 100.00
pwrmgr_same_csr_outstanding 0.740s 70.687us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
tl_intg_err 0 2 0.00
pwrmgr_sec_cm 0.720s 14.317us 0 1 0.00
pwrmgr_tl_intg_err 0.590s 10.353us 0 1 0.00
prim_count_check 0 1 0.00
pwrmgr_sec_cm 0.720s 14.317us 0 1 0.00
prim_fsm_check 0 1 0.00
pwrmgr_sec_cm 0.720s 14.317us 0 1 0.00
sec_cm_bus_integrity 0 1 0.00
pwrmgr_tl_intg_err 0.590s 10.353us 0 1 0.00
sec_cm_lc_ctrl_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_lc_ctrl_intersig_mubi 1.550s 789.286us 1 1 100.00
sec_cm_rom_ctrl_intersig_mubi 1 1 100.00
pwrmgr_wakeup_reset 0.690s 155.198us 1 1 100.00
sec_cm_rstmgr_intersig_mubi 1 1 100.00
pwrmgr_sec_cm_rstmgr_intersig_mubi 0.750s 46.921us 1 1 100.00
sec_cm_esc_rx_clk_bkgn_chk 1 1 100.00
pwrmgr_esc_clk_rst_malfunc 0.580s 30.478us 1 1 100.00
sec_cm_esc_rx_clk_local_esc 0 1 0.00
pwrmgr_sec_cm 0.720s 14.317us 0 1 0.00
sec_cm_fsm_sparse 0 1 0.00
pwrmgr_sec_cm 0.720s 14.317us 0 1 0.00
sec_cm_fsm_terminal 0 1 0.00
pwrmgr_sec_cm 0.720s 14.317us 0 1 0.00
sec_cm_ctrl_flow_global_esc 1 1 100.00
pwrmgr_global_esc 0.590s 95.031us 1 1 100.00
sec_cm_main_pd_rst_local_esc 1 1 100.00
pwrmgr_glitch 0.610s 34.587us 1 1 100.00
sec_cm_ctrl_config_regwen 1 1 100.00
pwrmgr_sec_cm_ctrl_config_regwen 0.790s 388.559us 1 1 100.00
sec_cm_wakeup_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.600s 42.322us 1 1 100.00
sec_cm_reset_config_regwen 1 1 100.00
pwrmgr_csr_rw 0.600s 42.322us 1 1 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
escalation_timeout 0 1 0.00
pwrmgr_escalation_timeout 0.750s 355.245us 0 1 0.00
stress_all_with_rand_reset 1 1 100.00
pwrmgr_stress_all_with_rand_reset 4.670s 1996.638us 1 1 100.00