Simulation Results: rom_ctrl

 
20/11/2025 19:30:26 sha: 1f7db17 json Branch: master Tool: vcs [unknown]
Coverage statistics
  • score
  • 96.8
  • line
  • 99.46
  • cond
  • 94.95
  • toggle
  • 99.41
  • fsm
  • 93.33
  • branch
  • 98.54
  • assert
  • 95.49
  • group
  • 96.42
Validation stages
V1
100.00%
V2
100.00%
V2S
66.67%
V3
100.00%
Testpoint Test Max Runtime Sim Time Pass Total %
smoke 2 2 100.00
rom_ctrl_smoke 6.850s 388.489us 2 2 100.00
csr_hw_reset 2 2 100.00
rom_ctrl_csr_hw_reset 9.730s 386.036us 2 2 100.00
csr_rw 2 2 100.00
rom_ctrl_csr_rw 6.520s 1025.619us 2 2 100.00
csr_bit_bash 2 2 100.00
rom_ctrl_csr_bit_bash 6.580s 3122.851us 2 2 100.00
csr_aliasing 2 2 100.00
rom_ctrl_csr_aliasing 5.350s 2785.058us 2 2 100.00
csr_mem_rw_with_rand_reset 2 2 100.00
rom_ctrl_csr_mem_rw_with_rand_reset 6.870s 305.329us 2 2 100.00
regwen_csr_and_corresponding_lockable_csr 4 4 100.00
rom_ctrl_csr_rw 6.520s 1025.619us 2 2 100.00
rom_ctrl_csr_aliasing 5.350s 2785.058us 2 2 100.00
mem_walk 2 2 100.00
rom_ctrl_mem_walk 7.280s 291.449us 2 2 100.00
mem_partial_access 2 2 100.00
rom_ctrl_mem_partial_access 6.560s 555.942us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
max_throughput_chk 2 2 100.00
rom_ctrl_max_throughput_chk 6.520s 470.198us 2 2 100.00
stress_all 2 2 100.00
rom_ctrl_stress_all 17.900s 3298.793us 2 2 100.00
kmac_err_chk 2 2 100.00
rom_ctrl_kmac_err_chk 13.920s 1087.131us 2 2 100.00
alert_test 2 2 100.00
rom_ctrl_alert_test 6.830s 543.995us 2 2 100.00
tl_d_oob_addr_access 2 2 100.00
rom_ctrl_tl_errors 8.300s 373.245us 2 2 100.00
tl_d_illegal_access 2 2 100.00
rom_ctrl_tl_errors 8.300s 373.245us 2 2 100.00
tl_d_outstanding_access 8 8 100.00
rom_ctrl_csr_hw_reset 9.730s 386.036us 2 2 100.00
rom_ctrl_csr_rw 6.520s 1025.619us 2 2 100.00
rom_ctrl_csr_aliasing 5.350s 2785.058us 2 2 100.00
rom_ctrl_same_csr_outstanding 7.010s 304.986us 2 2 100.00
tl_d_partial_access 8 8 100.00
rom_ctrl_csr_hw_reset 9.730s 386.036us 2 2 100.00
rom_ctrl_csr_rw 6.520s 1025.619us 2 2 100.00
rom_ctrl_csr_aliasing 5.350s 2785.058us 2 2 100.00
rom_ctrl_same_csr_outstanding 7.010s 304.986us 2 2 100.00
Testpoint Test Max Runtime Sim Time Pass Total %
corrupt_sig_fatal_chk 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 125.370s 27584.838us 1 2 50.00
passthru_mem_tl_intg_err 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.820s 1564.176us 2 2 100.00
tl_intg_err 3 4 75.00
rom_ctrl_tl_intg_err 93.150s 662.154us 2 2 100.00
rom_ctrl_sec_cm 223.430s 749.154us 1 2 50.00
prim_fsm_check 1 2 50.00
rom_ctrl_sec_cm 223.430s 749.154us 1 2 50.00
prim_count_check 1 2 50.00
rom_ctrl_sec_cm 223.430s 749.154us 1 2 50.00
sec_cm_checker_ctr_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 125.370s 27584.838us 1 2 50.00
sec_cm_checker_ctrl_flow_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 125.370s 27584.838us 1 2 50.00
sec_cm_checker_fsm_local_esc 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 125.370s 27584.838us 1 2 50.00
sec_cm_compare_ctrl_flow_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 125.370s 27584.838us 1 2 50.00
sec_cm_compare_ctr_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 125.370s 27584.838us 1 2 50.00
sec_cm_compare_ctr_redun 1 2 50.00
rom_ctrl_sec_cm 223.430s 749.154us 1 2 50.00
sec_cm_fsm_sparse 1 2 50.00
rom_ctrl_sec_cm 223.430s 749.154us 1 2 50.00
sec_cm_mem_scramble 2 2 100.00
rom_ctrl_smoke 6.850s 388.489us 2 2 100.00
sec_cm_mem_digest 2 2 100.00
rom_ctrl_smoke 6.850s 388.489us 2 2 100.00
sec_cm_intersig_mubi 2 2 100.00
rom_ctrl_smoke 6.850s 388.489us 2 2 100.00
sec_cm_bus_integrity 2 2 100.00
rom_ctrl_tl_intg_err 93.150s 662.154us 2 2 100.00
sec_cm_bus_local_esc 3 4 75.00
rom_ctrl_corrupt_sig_fatal_chk 125.370s 27584.838us 1 2 50.00
rom_ctrl_kmac_err_chk 13.920s 1087.131us 2 2 100.00
sec_cm_mux_mubi 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 125.370s 27584.838us 1 2 50.00
sec_cm_mux_consistency 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 125.370s 27584.838us 1 2 50.00
sec_cm_ctrl_redun 1 2 50.00
rom_ctrl_corrupt_sig_fatal_chk 125.370s 27584.838us 1 2 50.00
sec_cm_ctrl_mem_integrity 2 2 100.00
rom_ctrl_passthru_mem_tl_intg_err 39.820s 1564.176us 2 2 100.00
sec_cm_tlul_fifo_ctr_redun 1 2 50.00
rom_ctrl_sec_cm 223.430s 749.154us 1 2 50.00
Testpoint Test Max Runtime Sim Time Pass Total %
stress_all_with_rand_reset 2 2 100.00
rom_ctrl_stress_all_with_rand_reset 152.450s 39551.195us 2 2 100.00